netdev - Re: [PATCH 3/5 v2] net/cpsw: don't rely only on netif_running() to check which device is active

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Message-ID: <51750D1B.4060600@ti.com>
Date:	Mon, 22 Apr 2013 15:42:43 +0530
From:	Mugunthan V N <mugunthanvnm@...com>
To:	Sebastian Andrzej Siewior <bigeasy@...utronix.de>
CC:	<netdev@...r.kernel.org>, <tglx@...utronix.de>,
	"David S. Miller" <davem@...emloft.net>
Subject: Re: [PATCH 3/5 v2] net/cpsw: don't rely only on netif_running() to
 check which device is active

On 4/22/2013 3:19 PM, Sebastian Andrzej Siewior wrote:
> On 04/22/2013 11:40 AM, Mugunthan V N wrote:
>> Yes, when interrupt is disabled in hardware then interrupt must be
>> disabled in
> here is a word missing and I can't figure it out.
>
>> my initial days i have verified it, CPSW doesn't allow any new
>> interrupts to
>> propagate  to arm if CPSW interrupt is disabled but there is an issue.
> Not completed i.e. outstanding I think.
>
>> CPSW irq
>> signal is not directly connected to irq controller, it is connected via
>> edge to
>> level conversion so if one interrupt reaches arm, irq controller has to be
>> disabled else arm get blocked in CPSW ISR.
> Okay. Is there an errata document describing this behavior? If the CPSW
> interrupt source is disabled, the CPSW should keep quiet. This is also
> what the manual says. If cpsw does not allow new interrupts to
> propagate to ARM's INTC then there is something wrong. It looks like
> the source is not disabled in CPSW properly. This works on ES1.0.
>
> Lets get back to this ofter this series of five is merged.
>
Sorry there was a formatting issue...

Yes, when interrupt is disabled in hardware then interrupt must be disabled.
In my initial days i have verified it, CPSW doesn't allow any new 
interrupts to
propagate  to arm if CPSW interrupt is disabled which is correct. CPSW irq
signal is not directly connected to irq controller, it is connected via 
edge to
level conversion so it is a kind of latched interrupt and so the 
interrupt has
to be disabled in interrupt controller to disable the interrupt, else 
arm get
blocked in CPSW ISR.

This behavior is not only in AM335x CPSW, it is as is from its previous
versions in TI814x and TI8107.

Regards
Mugunthan V N
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