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Message-ID: <1367495531-19470-1-git-send-email-mugunthanvnm@ti.com>
Date:	Thu, 2 May 2013 17:22:11 +0530
From:	Mugunthan V N <mugunthanvnm@...com>
To:	<netdev@...r.kernel.org>
CC:	<davem@...emloft.net>, <linux-omap@...r.kernel.org>,
	Mugunthan V N <mugunthanvnm@...com>,
	Sebastian Siewior <bigeasy@...utronix.de>
Subject: [net-next PATCH 1/1] drivers: net: cpsw: irq not disabled in cpsw isr in particular sequence

In CPSW NAPI, after processing all interrupts IRQ is enabled and then book
keeping irq_enabled is updated. In random cases when a packet is transmitted
or received between processing packets and IRQ enabled, then just after
enabled IRQ and before irq_enabled is updated, ISR is called so IRQs are
not disabled as irq_enabled is still false and CPU gets locked in CPSW ISR.

By changing the sequence as update the irq_enabled and then enable IRQ
fixes the issue. This issue is not captured always as it is a timing issue
whether Tx or Rx IRQ is invoked between packet processing and enable IRQ.

Cc: Sebastian Siewior <bigeasy@...utronix.de>
Signed-off-by: Mugunthan V N <mugunthanvnm@...com>
---
 drivers/net/ethernet/ti/cpsw.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 59c4391..21a5b29 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -555,8 +555,8 @@ static int cpsw_poll(struct napi_struct *napi, int budget)
 		cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 		prim_cpsw = cpsw_get_slave_priv(priv, 0);
 		if (prim_cpsw->irq_enabled == false) {
-			cpsw_enable_irq(priv);
 			prim_cpsw->irq_enabled = true;
+			cpsw_enable_irq(priv);
 		}
 	}
 
-- 
1.7.9.5

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