netdev - Re: [PATCH v2] emac: Fix EMAC soft reset on 460EX/GT

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Message-Id: <20130511.174039.1747680568639795324.davem@davemloft.net>
Date:	Sat, 11 May 2013 17:40:39 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	pgynther@...gle.com
Cc:	netdev@...r.kernel.org
Subject: Re: [PATCH v2] emac: Fix EMAC soft reset on 460EX/GT

From: Petri Gynther <pgynther@...gle.com>
Date: Thu, 9 May 2013 19:50:00 -0700

> Fix EMAC soft reset on 460EX/GT to select the right PHY clock source
> before and after the soft reset.
> 
> EMAC with PHY should use the clock from PHY during soft reset.
> EMAC without PHY should use the internal clock during soft reset.
> 
> PPC460EX/GT Embedded Processor Advanced User's Manual
> section 28.10.1 Mode Register 0 (EMACx_MR0) states:
> Note: The PHY must provide a TX Clk in order to perform a soft reset
> of the EMAC. If none is present, select the internal clock
> (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1).
> After a soft reset, select the external clock.
> 
> Without the fix, 460EX/GT-based boards with RGMII PHYs attached to
> EMACs experience EMAC interrupt storm and system watchdog reset when
> issuing "ifconfig eth0 down" + "ifconfig eth0 up" a few times.
> The system enters endless loop of serving emac_irq() with EMACx_ISR
> register stuck at value 0x10000000 (Rx parity error).
> 
> With the fix, the above issue is no longer observed.
> 
> Signed-off-by: Petri Gynther <pgynther@...gle.com>

Applied.
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