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Message-ID: <20130523175357.GB2821@obsidianresearch.com>
Date: Thu, 23 May 2013 11:53:57 -0600
From: Jason Gunthorpe <jgunthorpe@...idianresearch.com>
To: Jason Cooper <jason@...edaemon.net>
Cc: Andrew Lunn <andrew@...n.ch>, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
linuxppc-dev@...ts.ozlabs.org, David Miller <davem@...emloft.net>,
Lennert Buytenhek <buytenh@...tstofly.org>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Subject: Re: [PATCH 2/2] net: mv643xx_eth: proper initialization for Kirkwood
SoCs
On Thu, May 23, 2013 at 01:23:39PM -0400, Jason Cooper wrote:
> Shouldn't it rather be
>
> compatible = "marvell,kirkwood-eth", "marvell,orion-eth";
Not sure about orion-eth?
> I'm inclined to go with of_machine_is_compatible() since the only
> concrete difference we know is that the tweak is needed on kirkwood and
> nowhere else.
But there is a larger problem here then just this one bit.
The PSC1 register must be set properly for the board layout, and today
we rely on the bootloader to set it. In fact, even with Sebastian's
change the ethernet port won't work without bootloader
intervention. The PortReset bit should also be cleared by the driver
(and it is only present on some variants of this IP block,
apparently).
We know that some Marvell SOC's wack the ethernet registers when they
clock gate, and the flip of Clk125Bypass is another symptom of this
general problem.
So, long term, the PSC1 must be fully set by the driver, based on DT
information describing the board (eg RGMII/MII/1000Base-X [SFP] Phy
type), and the layout of this register seems to vary on a SOC by SOC
basis.
Thus, I think it is appropriate to call this variant of the eth IP
'marvell,kirkwood-eth' which indicates that the register block follows
the kirkwood manual and the PSC1 register specifically has the
kirkwood layout.
The question is what other Marvell SOCs have the same PSC1 layout as
kirkwood?
Jason
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