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Date:	Sun, 26 May 2013 12:39:00 +0200
From:	Richard Cochran <>
To:	Matthew Vick <>
Subject: igb: acknowledging time sync interrupts


In igb_main.c you have ISR code like:

	if (icr & E1000_ICR_TS) {
		u32 tsicr = rd32(E1000_TSICR);

		if (tsicr & E1000_TSICR_TXTS) {
			/* acknowledge the interrupt */
			wr32(E1000_TSICR, E1000_TSICR_TXTS);
			/* retrieve hardware timestamp */

In the datasheet for the 82580 and the i210, for TSICR it says,

   Note: Once ICR.Time_Sync is set, the internal value of this
         register should be cleared by writing 1b to all bits
         or cleared by a read to enable receiving an additional
         ICR.Time_Sync interrupt.

and that implies that your write to acknowledge the interrupt is
superfluous, since you already read the TSICR.

Is this an error in the datasheets, or is the code doing extra,
unneeded work?


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