netdev - Re: [PATCH v2] net: ethernet: xilinx_emaclite: set protocol selector bits when writing ANAR

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Message-Id: <20130531.172654.1594446064482575081.davem@davemloft.net>
Date:	Fri, 31 May 2013 17:26:54 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	renner@...-gmbh.de
Cc:	netdev@...r.kernel.org, monstr@...str.eu
Subject: Re: [PATCH v2] net: ethernet: xilinx_emaclite: set protocol
 selector bits when writing ANAR

From: "renner@...-gmbh.de" <renner@...-gmbh.de>
Date: Thu, 30 May 2013 00:36:18 +0200 (CEST)

> This patch sets the protocol selector bits (4:0) of the PHY's MII_ADVERTISE
> register (ANAR) when writing ADVERTISE_ALL. The protocol selector bits are
> indicating IEEE 803.3u support and are fixed / read-only on some PHYs. Not
> setting them correctly on others (like TI DP83630) makes the PHY fall back
> to 10M HDX mode which should be avoided.
> 
> Tested for TI DP83630 PHY on Microblaze platform.
> 
> Signed-off-by: Jens Renner <renner@...-gmbh.de>

This patch has been corrupted by your email client, among other things it
has corrupted the whitespace in the patch, changing TAB characters into
sequences of spaces.

Please read Documentation/email-clients.txt in the kernel sources, and then
send a test patch to yourself.  Do not resubmit this patch to the list until
you can successfully apply the test patch you email to yourself.

Thanks.
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