netdev - Re: [PATCH v3] net: ethernet: xilinx_emaclite: set protocol selector bits when writing ANAR

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Message-ID: <51AC6412.5090202@monstr.eu>
Date:	Mon, 03 Jun 2013 11:38:26 +0200
From:	Michal Simek <monstr@...str.eu>
To:	"Jens Renner (EFE)" <renner@...-gmbh.de>
CC:	netdev@...r.kernel.org
Subject: Re: [PATCH v3] net: ethernet: xilinx_emaclite: set protocol selector
 bits when writing ANAR

On 06/02/2013 05:36 PM, Jens Renner (EFE) wrote:
> This patch sets the protocol selector bits (4:0) of the PHY's MII_ADVERTISE
> register (ANAR) when writing ADVERTISE_ALL. The protocol selector bits are
> indicating IEEE 803.3u support and are fixed / read-only on some PHYs. Not
> setting them correctly on others (like TI DP83630) makes the PHY fall back
> to 10M HDX mode which should be avoided.
> 
> Tested for TI DP83630 PHY on Microblaze platform.
> 
> Signed-off-by: Jens Renner <renner@...-gmbh.de>

You should probably fix this line too.

Thanks,
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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