netdev - Re: [PATCH RFC] reciprocal_divide: correction/update of the algorithm

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Message-ID: <1389729032.31367.262.camel@edumazet-glaptop2.roam.corp.google.com>
Date:	Tue, 14 Jan 2014 11:50:32 -0800
From:	Eric Dumazet <eric.dumazet@...il.com>
To:	Austin S Hemmelgarn <ahferroin7@...il.com>
Cc:	Hannes Frederic Sowa <hannes@...essinduktion.org>,
	netdev@...r.kernel.org, dborkman@...hat.com,
	linux-kernel@...r.kernel.org, darkjames-ws@...kjames.pl
Subject: Re: [PATCH RFC] reciprocal_divide: correction/update of the
 algorithm

On Tue, 2014-01-14 at 14:22 -0500, Austin S Hemmelgarn wrote:

> I disagree with the statement that current CPU's have reasonably fast
> dividers.  A lot of embedded processors and many low-end x86 CPU's do
> not in-fact have any hardware divider, and usually provide it using
> microcode based emulation if they provide it at all.  The AMD Jaguar
> micro-architecture in particular comes to mind, it uses an iterative
> division algorithm provided by the microcode that only produces 2 bits
> of quotient per cycle, even in the best case (2 8-bit integers and an
> integral 8-bit quotient) this still takes 4 cycles, which is twice as
> slow as any other math operation on the same processor.

I doubt you run any BPF filter with a divide instruction in it on these
platform.

Get real, do not over optimize things where it does not matter.



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