netdev - Re: [PATCH v5] can: add Renesas R-Car CAN driver

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Date:	Fri, 28 Feb 2014 10:08:46 +0100
From:	Marc Kleine-Budde <mkl@...gutronix.de>
To:	Sergei Shtylyov <sergei.shtylyov@...entembedded.com>,
	netdev@...r.kernel.org, wg@...ndegger.com,
	linux-can@...r.kernel.org
CC:	linux-sh@...r.kernel.org, vksavl@...il.com
Subject: Re: [PATCH v5] can: add Renesas R-Car CAN driver

On 02/21/2014 12:48 AM, Sergei Shtylyov wrote:

>>> 1. According to documentation BCR is the 24-bit register.
>>> Actually we can consider some 32-bit register that combines BCR and
>>> CLKR but according to documentation there are two separate registers.
>>> 2. BCR has 8- ,16-, and 32-bit access (according to documentation).
>>> 3. This is the algorithm that the documentation suggests.
>>> 4. We had a driver version with byte access but 32-bit access seems
>>> shorter.
> 
>> Please use a normal read-modify-write 32 bit access.
> 
>    IMO, reading 32-bits is futile, as we're going to completely
> overwrite those 24 bits that constitute BCR. So I kept the 8-bit CLKR
> read but removed the CLKR write in the end. I've also added a comment
> clarifying why CLKR is positioned in the LSBs of 32-bit word (while it's
> address would assume MSBs).
> The host bus is big-endian but byte-swaps at least 16- and 32-bit
> accesses, so that read[wl]()/write[wl]() work. 8-bit accesses are not
> byte swapped, despite what the figure in the manual shows.

A 32 bit read/modify/write is a standard operation, nothing special, no
need to worry about byte swapping or anything like this.

Marc

-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
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