netdev - Re: [PATCH v5] can: add Renesas R-Car CAN driver

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Date:	Fri, 28 Feb 2014 12:50:55 +0100
From:	Marc Kleine-Budde <mkl@...gutronix.de>
To:	David Laight <David.Laight@...LAB.COM>,
	'Geert Uytterhoeven' <geert@...ux-m68k.org>
CC:	Sergei Shtylyov <sergei.shtylyov@...entembedded.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"wg@...ndegger.com" <wg@...ndegger.com>,
	"linux-can@...r.kernel.org" <linux-can@...r.kernel.org>,
	Linux-sh list <linux-sh@...r.kernel.org>,
	Pavel Kiryukhin <vksavl@...il.com>
Subject: Re: [PATCH v5] can: add Renesas R-Car CAN driver

On 02/28/2014 12:47 PM, David Laight wrote:
> From: Geert Uytterhoeven
>> On Fri, Feb 28, 2014 at 12:37 PM, Marc Kleine-Budde <mkl@...gutronix.de> wrote:
>>>>> A 32 bit read/modify/write is a standard operation, nothing special, no
>>>>> need to worry about byte swapping or anything like this.
>>>>
>>>>    Oh, really? 8-)
>>>>    Don't you know that read[bwlq]() assume little-endian memory layout
>>>> and to read from big-endian 32-bit register one normally needs readl_be()?
>>>
>>> I assume you are on little endian ARM only (for now).
>>>
>>> If you use a standard 32 bit read, then modify the correct bits in that
>>> 32 bit word and write it back, with the corresponding 32 bit write
>>> everything should be fine. For this usecase you just have yo figure out
>>> which 24 of the 32 bit are the one you have to change and which are the
>>> 8 that must not be modified.
>>>
>>> Looking at the register layout:
>>>
>>>> +     u8 bcr[3];      /* Bit Configuration Register */
>>>> +     u8 clkr;        /* Clock Select Register */
>>>
>>> I think clkr would be the lowest 8 bit and bcr[] are the upper 24.
>>
>> That would be the outcome on big endian ;-)
> 
> Looks to me as though it should be defined as a 32bit field and then
> the appropriate bit definitions and masks applied.

Ack, 32bit yes, but no field (as in http://en.wikipedia.org/wiki/Bit_field).

Marc
-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
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