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Message-Id: <1393792922-2381-2-git-send-email-vbridgers2013@gmail.com>
Date: Sun, 2 Mar 2014 14:42:00 -0600
From: Vince Bridgers <vbridgers2013@...il.com>
To: devicetree@...r.kernel.org, netdev@...r.kernel.org,
linux-doc@...r.kernel.org
Cc: robh+dt@...nel.org, pawel.moll@....com, mark.rutland@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
rob@...dley.net, vbridgers2013@...il.com
Subject: [PATCH RFC 1/3] dts: Add bindings for the Altera Triple Speed Ethernet Driver
This patch adds a bindings description for the Altera Triple Speed Ethernet
(TSE) driver. The bindings support the legacy SGDMA soft IP as well as the
preferred MSGDMA soft IP. The TSE can be configured and synthesized in soft
logic using Altera's Quartus toolchain. Please consult the bindings document
for supported options.
Signed-off-by: Vince Bridgers <vbridgers2013@...il.com>
---
.../devicetree/bindings/net/altera_tse.txt | 114 ++++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/altera_tse.txt
diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt
new file mode 100644
index 0000000..b53d972
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/altera_tse.txt
@@ -0,0 +1,114 @@
+* Altera Triple-Speed Ethernet MAC driver (TSE)
+
+Required properties:
+- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
+ be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
+ Compatiblilty string matches are case insenstive; so legacy
+ device trees using ALTR will be supported.
+- reg: Address and length of the register set for the device. It contains
+ the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+ "control_port": MAC configuration space region
+ "tx_csr": xDMA Tx dispatcher control and status space region
+ "tx_desc": MSGDMA Tx dispatcher descriptor space region
+ "rx_csr" : xDMA Rx dispatcher control and status space region
+ "rx_desc": MSGDMA Rx dispatcher descriptor space region
+ "rx_resp": MSGDMA Rx dispatcher response space region
+ "s1": SGDMA descriptor memory
+- interrupts: Should contain the TSE interrupts
+- interrupt-names: Should contain the interrupt names
+ "rx_irq": xDMA Rx dispatcher interrupt
+ "tx_irq": xDMA Tx dispatcher interrupt
+- altr,rx-fifo-depth: MAC receive FIFO buffer depth (in 32-bit words)
+- altr,tx-fifo-depth: MAC transmit FIFO buffer depth (in 32-bit words)
+- phy-mode: String, operation mode of the PHY interface. Supported values are:
+ "mii", "gmii", "rgmii-id", "rgmii", "sgmii"
+- phy-handle: A phandle pointing to device tree node with
+ device_type = "ethernet-phy". Using a phandle allows
+ support for both phys connected to TSE's local mdio or
+ some other phy.
+- altr,phy-addr: PHY address to use with a phy connected to TSE's local mdio.
+ One should have either a phy-handle property or altr,phy-addr
+ when using a phy with the TSE.
+
+-mdio device tree subnode: When the TSE has a phy connected to its local
+ mdio, there must be device tree subnode with the following
+ required properties:
+
+ - compatible: Must be "altr,tse-mdio".
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
+
+ For each phy on the mdio bus, there must be a node with the following
+ fields:
+
+ - reg: phy id used to communicate to phy.
+ - device_type: Must be "ethernet-phy".
+
+Optional properties:
+- local-mac-address: 6 bytes, ethernet mac address to use
+
+Example:
+
+ tse_sub_0_eth_tse_0: ethernet@...00000000 {
+ compatible = "altr,tse-msgdma-1.0";
+ reg = < 0x00000001 0x00000000 0x00000400
+ 0x00000001 0x00000460 0x00000020
+ 0x00000001 0x00000480 0x00000020
+ 0x00000001 0x000004A0 0x00000008
+ 0x00000001 0x00000400 0x00000020
+ 0x00000001 0x00000420 0x00000020 >;
+ reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
+ interrupt-parent = < &hps_0_arm_gic_0 >;
+ interrupts = < 0 41 4 0 40 4 >;
+ interrupt-names = "rx_irq", "tx_irq";
+ altr,rx-fifo-depth = < 2048 >;
+ altr,tx-fifo-depth = < 2048 >;
+ address-bits = < 48 >;
+ max-frame-size = < 1500 >;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ phy-mode = "gmii";
+ altr,enable-sup-addr = < 0 >;
+ altr,enable-hash = < 1 >;
+ phy-handle = < &phy0 >;
+ mdio@0 {
+ compatible = "altr,tse-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+
+ };
+ };
+
+ tse_sub_1_eth_tse_0: ethernet@...00001000 {
+ compatible = "altr,tse-msgdma-1.0";
+ reg = < 0x00000001 0x00001000 0x00000400
+ 0x00000001 0x00001460 0x00000020
+ 0x00000001 0x00001480 0x00000020
+ 0x00000001 0x000014A0 0x00000008
+ 0x00000001 0x00001400 0x00000020
+ 0x00000001 0x00001420 0x00000020 >;
+ reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
+ interrupt-parent = < &hps_0_arm_gic_0 >;
+ interrupts = < 0 43 4 0 42 4 >;
+ interrupt-names = "rx_irq", "tx_irq";
+ altr,rx-fifo-depth = < 2048 >;
+ altr,tx-fifo-depth = < 2048 >;
+ address-bits = < 48 >;
+ max-frame-size = < 1500 >;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ phy-mode = "gmii";
+ altr,phy-addr = < 1 >;
+ altr,enable-sup-addr = < 0 >;
+ altr,enable-hash = < 1 >;
+ phy-handle = < &phy1 >;
+ };
+
--
1.7.9.5
--
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