lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAD6G_RR=y+myvtEpa3YKiOx_8LR=Ad_nHUxuaXKakfKKyjuEaw@mail.gmail.com>
Date:	Wed, 5 Mar 2014 11:43:26 +0530
From:	Jagan Teki <jagannadh.teki@...il.com>
To:	Michael Chan <mchan@...adcom.com>
Cc:	netdev@...r.kernel.org,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	Nithin Nayak Sujir <nsujir@...adcom.com>,
	Grant Likely <grant.likely@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: sblk->status_tag on drivers/net/ethernet/broadcom/tg3.c

Hi Michael,

Thanks for your inputs.

On Wed, Mar 5, 2014 at 9:42 AM, Michael Chan <mchan@...adcom.com> wrote:
> On Wed, 2014-03-05 at 09:33 +0530, Jagan Teki wrote:
>> The driver is not seeing the status block mean - tg3.c driver?
>
> Yes, tg3 driver.  All IRQ events (link change, rx, tx) are in status
> block.  If tg3 does not see the correct bits and indexes in the status
> block, it won't know what to do.  In this case, it doesn't see the link
> change bit in status block (I suspect), so it is not acknowledging and
> clearing the link change event.  Status block is DMA'ed from the NIC to
> memory.

OK.

As per your point I've a question here like - the status block is not properly
updated (DMA'ed), does this depends on the address range we are advertised
on PCIe ranges filed to make sure to use EP-
http://devicetree.org/Device_Tree_Usage#PCI_Host_Bridge

The reason for asking this is we have two kind of PCIe bridge in separate
boards where one is working fine by showing below log, and other
we could see this issue.

# ifconfig eth0 172.16.0.2 up
RC: handler
tg3_interrupt_tagged: ++status_tag = 0x1 write status = 0x1
--status_tag = 0x1
RC: handler
tg3_interrupt_tagged: ++status_tag = 0x1 write status = 0x1
--status_tag = 0x1 tg3_poll: tag = 0x1 calling tg3_int_reenable val =
0x01000000

>
>> Does it relates to ISR or addressing of PCIe RC driver, I'm doing
>> nothing on my PCIe RC driver just read the legacy INT# status and
>> return.
>
> RC stands for what?  Root Complex?  I don't know what an RC driver does.

Yes, Root Complex driver in PCIe bridge.

-- 
Jagan.
--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ