netdev - Re: [PATCH v5] can: xilinx CAN controller support.

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Date:	Mon, 10 Mar 2014 16:04:51 +0100
From:	Michal Simek <monstr@...str.eu>
To:	Marc Kleine-Budde <mkl@...gutronix.de>
CC:	Kedareswara rao Appana <appana.durga.rao@...inx.com>,
	wg@...ndegger.com, michal.simek@...inx.com,
	grant.likely@...aro.org, robh+dt@...nel.org,
	linux-can@...r.kernel.org, netdev@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	Kedareswara rao Appana <appanad@...inx.com>
Subject: Re: [PATCH v5] can: xilinx CAN controller support.

Hi Marc,

On 03/10/2014 03:57 PM, Marc Kleine-Budde wrote:
> On 03/04/2014 02:20 PM, Kedareswara rao Appana wrote:
>> This patch adds xilinx CAN controller support.
>> This driver supports both ZYNQ CANPS and Soft IP
>> AXI CAN controller.
>>
>> Signed-off-by: Kedareswara rao Appana <appanad@...inx.com>
>> ---
>> This patch is rebased on the 3.14 rc5 kernel.
>> Changes for v5:
>> - Updated the driver with the review comments.
>> - Remove the check for the tx fifo full interrupt condition
>>   form Tx interrupt routine as we are checking it in the _xmit
>>   routine.
>> - Clearing the txok interrupt in the tx interrupt routine for
>>   every Tx can frame.
>> Changes for v4:
>> - Added check for the tx fifo full interrupt condition in
>>   Tx interrupt routine.
>> - Added be iohelper functions.
>> - Moved the clock enable/disable to probe/remove because of
>>   Added big endian support for AXI CAN controller case(reading
>>   a register during probe for that we need to enable clock).
>> Changes for v3:
>> - Updated the driver with the review comments.
>> - Modified the tranmit logic as per Marc suggestion.
>> - Enabling the clock when the interface is up to reduce the
>>   Power consumption.
>> Changes for v2:
>> - Updated with the review comments.
>> - Removed the unnecessary debug prints.
>> - include tx,rx fifo depths in ZYNQ CANPS case also.
>> ---
>>  .../devicetree/bindings/net/can/xilinx_can.txt     |   45 +
>>  drivers/net/can/Kconfig                            |    7 +
>>  drivers/net/can/Makefile                           |    1 +
>>  drivers/net/can/xilinx_can.c                       | 1195 ++++++++++++++++++++
>>  4 files changed, 1248 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/net/can/xilinx_can.txt
>>  create mode 100644 drivers/net/can/xilinx_can.c
>>
>> diff --git a/Documentation/devicetree/bindings/net/can/xilinx_can.txt b/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>> new file mode 100644
>> index 0000000..0e57103
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/can/xilinx_can.txt
>> @@ -0,0 +1,45 @@
>> +Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
>> +---------------------------------------------------------
>> +
>> +Required properties:
>> +- compatible		: Should be "xlnx,zynq-can-1.00.a" for Zynq CAN
>> +			  controllers and "xlnx,axi-can-1.00.a" for Axi CAN
>> +			  controllers.
>> +- reg			: Physical base address and size of the Axi CAN/Zynq
>> +			  CANPS registers map.
>> +- interrupts		: Property with a value describing the interrupt
>> +			  number.
>> +- interrupt-parent	: Must be core interrupt controller
>> +- clock-names		: List of input clock names - "ref_clk", "aper_clk"
>> +			  (See clock bindings for details. Two clocks are
>> +			   required for Zynq CAN. For Axi CAN
>> +			   case it is one(ref_clk)).
>> +- clocks		: Clock phandles (see clock bindings for details).
>> +- tx-fifo-depth		: Can Tx fifo depth.
>> +- rx-fifo-depth		: Can Rx fifo depth.
>> +
>> +
>> +Example:
>> +
>> +For Zynq CANPS Dts file:
>> +	zynq_can_0: zynq-can@...08000 {
>> +			compatible = "xlnx,zynq-can-1.00.a";
>> +			clocks = <&clkc 19>, <&clkc 36>;
>> +			clock-names = "ref_clk", "aper_clk";
>> +			reg = <0xe0008000 0x1000>;
>> +			interrupts = <0 28 4>;
>> +			interrupt-parent = <&intc>;
>> +			tx-fifo-depth = <0x40>;
>> +			rx-fifo-depth = <0x40>;
>> +		};
>> +For Axi CAN Dts file:
>> +	axi_can_0: axi-can@...00000 {
>> +			compatible = "xlnx,axi-can-1.00.a";
>> +			clocks = <&clkc 0>;
>> +			clock-names = "ref_clk" ;
>> +			reg = <0x40000000 0x10000>;
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <0 59 1>;
>> +			tx-fifo-depth = <0x40>;
>> +			rx-fifo-depth = <0x40>;
>> +		};
>> diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
>> index 9e7d95d..b180239 100644
>> --- a/drivers/net/can/Kconfig
>> +++ b/drivers/net/can/Kconfig
>> @@ -125,6 +125,13 @@ config CAN_GRCAN
>>  	  endian syntheses of the cores would need some modifications on
>>  	  the hardware level to work.
>>  
>> +config CAN_XILINXCAN
>> +	tristate "Xilinx CAN"
>> +	depends on ARCH_ZYNQ || MICROBLAZE
> 
> Is Zynq multiarch already?

let me just answer this. Zynq is device with hardcoded dual arm cortex-a9 + some IPs
and programmable logic.
It means if you add Microblaze to PL or another CPU then you get multi architecture setup.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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