netdev - Re: [patch net-next RFC 0/4] introduce infrastructure for support of switch chip datapath

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Message-ID: <53335A7F.8010801@mojatatu.com>
Date:	Wed, 26 Mar 2014 18:53:51 -0400
From:	Jamal Hadi Salim <jhs@...atatu.com>
To:	Florian Fainelli <f.fainelli@...il.com>
CC:	Jiri Pirko <jiri@...nulli.us>,
	Roopa Prabhu <roopa@...ulusnetworks.com>,
	Neil Horman <nhorman@...driver.com>,
	Thomas Graf <tgraf@...g.ch>, netdev <netdev@...r.kernel.org>,
	David Miller <davem@...emloft.net>,
	Andy Gospodarek <andy@...yhouse.net>,
	dborkman <dborkman@...hat.com>, ogerlitz <ogerlitz@...lanox.com>,
	jesse <jesse@...ira.com>, pshelar <pshelar@...ira.com>,
	azhou <azhou@...ira.com>, Ben Hutchings <ben@...adent.org.uk>,
	Stephen Hemminger <stephen@...workplumber.org>,
	jeffrey.t.kirsher@...el.com, vyasevic <vyasevic@...hat.com>,
	Cong Wang <xiyou.wangcong@...il.com>,
	John Fastabend <john.r.fastabend@...el.com>,
	Eric Dumazet <edumazet@...gle.com>,
	Scott Feldman <sfeldma@...ulusnetworks.com>,
	Lennert Buytenhek <buytenh@...tstofly.org>,
	Shrijeet Mukherjee <shm@...ulusnetworks.com>,
	Felix Fietkau <nbd@...nwrt.org>
Subject: Re: [patch net-next RFC 0/4] introduce infrastructure for support
 of switch chip datapath

On 03/26/14 18:22, Florian Fainelli wrote:
> 2014-03-26 14:51 GMT-07:00 Jamal Hadi Salim <jhs@...atatu.com>:

>
> eth0 corresponds to a CPU Ethernet MAC facing e.g: sw1p3 switch port.
> It is "regular" Ethernet driver connected to the switch without
> switch-specific logic. The goal is twofold:
>
> - allow any regular Ethernet driver to be connected to an external
> switch via e.g: MDIO/MDC or other without specific switch knowledge
> - represents accurately how the hardware is designed/connected
>

Gah. Sorry - I missed the MII interface.
In such a case as shown here then, how do you control sw1p0-3?

> but maybe, we can simplify and have e.g: sw1p3 and eth0 be the same interface...

It sounds to me the CPU side is only a driver for sw1p3.

>>
>> Note: even the high end chips tend to have the concept of a "cpu port"
>> but my experience is to hide that as part of the switch driver.

Note: the high end devices "cpu ports" are accessible typically
via PCIE interfaces for control and some DMA for data activity.

cheers,
jamal


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