netdev - Re: [patch net-next RFC 0/4] introduce infrastructure for support of switch chip datapath

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Date:	Wed, 26 Mar 2014 08:21:48 +0100
From:	Jiri Pirko <jiri@...nulli.us>
To:	Thomas Graf <tgraf@...g.ch>
Cc:	Jamal Hadi Salim <jhs@...atatu.com>,
	Neil Horman <nhorman@...driver.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	netdev <netdev@...r.kernel.org>,
	David Miller <davem@...emloft.net>, andy@...yhouse.net,
	dborkman@...hat.com, ogerlitz@...lanox.com, jesse@...ira.com,
	pshelar@...ira.com, azhou@...ira.com,
	Ben Hutchings <ben@...adent.org.uk>,
	Stephen Hemminger <stephen@...workplumber.org>,
	jeffrey.t.kirsher@...el.com, vyasevic <vyasevic@...hat.com>,
	Cong Wang <xiyou.wangcong@...il.com>,
	John Fastabend <john.r.fastabend@...el.com>,
	Eric Dumazet <edumazet@...gle.com>,
	Scott Feldman <sfeldma@...ulusnetworks.com>,
	Lennert Buytenhek <buytenh@...tstofly.org>
Subject: Re: [patch net-next RFC 0/4] introduce infrastructure for support of
 switch chip datapath

Tue, Mar 25, 2014 at 10:19:45PM CET, tgraf@...g.ch wrote:
>On 03/25/14 at 04:56pm, Jamal Hadi Salim wrote:
>> On 03/25/14 15:35, Neil Horman wrote:
>> >1) ip link show:
>> >em1
>> >sw1
>> >
>> >2) ip link show sw1
>> >sw1
>> >
>> >3) ip link show -p sw1
>> >sw1p0
>> >sw1p1
>> >sw1p2...
>> >
>> >
>> >The idea is to augment user space to allow the visibiliy of ports through the
>> >switch device, not directly, but using the same existing mechanisms.  We can
>> >reuse all the existing infrastruture, but with this model, control must pass
>> >through the switch device driver, allowing it to taylor available features by
>> >passing the netlink request on to the appropriate netdevice, or sending back an
>> >error itself.
>> >
>> 
>> I think i am with you mostly - just not on the visibility of a "master"
>> device.
>> Expose the ports. Users create bridges bonds and if the hardware is
>> capable it does the hard work to ensure consistency. No change in tools.

Creating bonding of the switch ports does not fit into the picture at
all. These port netdevices are just a representation of a port. Not
actual netdevice where the data goes through.

Please consider the case I gave already to this thread:

        switch chip
   ------------------------
    |  |  |  |  |  |   |               CPU
   p1 p2 ...pn px py  MNGMNT       -----------
                |  |   |              pcie
                |  |   |         ---------------
                |  |   |          |  NIC0 NIC1
                |  |   ---pcie-----   |   |
                |  ------someMII-------   |
                ---------someMII-----------

        NIC0 and NIC1 are ordinary NICs like 8139too for example with no
        notion they are connected to a switch. They as completely
        independent on the mngmnt iface.


There, actual data is coming through NIC0 and NIC1 which is completely separated
from the p1...pn,px.px port representations.

And if you understand it this way, it makes perfect sense to have a master device
for these port representations.

Btw note this model fits into existing DSA as well I believe. The actual DSA
devices whould act as NIC0, NIC1 and what would be added is the switch
representation (couple of more netdevices to represent actual HW ports and
their master)

>
>Exactly. This is what I meant as well. No change in tools.

I agree.

>
>It's not just about changing ip link. We have tons of existing
>applications out there using Netlink and they will expect all ports
>visible if they issue RTM_GETLINK with NLM_F_DUMP.
>
>What speaks against exposing it by default? To me, the model should
>not differ from a multi port NIC which we also expose all ports with
>any indirection.

Note that you won't get actual data through these ports (visible to
CPU). That is where it differs from multiport NIC.
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