netdev - Re: [PATCH v7 1/2] can: xilinx CAN controller support

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Date:	Mon, 07 Apr 2014 08:56:50 +0200
From:	Michal Simek <monstr@...str.eu>
To:	Kedareswara rao Appana <appana.durga.rao@...inx.com>
CC:	wg@...ndegger.com, mkl@...gutronix.de, michal.simek@...inx.com,
	grant.likely@...aro.org, robh+dt@...nel.org,
	linux-can@...r.kernel.org, netdev@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	Kedareswara rao Appana <appanad@...inx.com>
Subject: Re: [PATCH v7 1/2] can: xilinx CAN controller support

On 04/02/2014 03:13 PM, Kedareswara rao Appana wrote:
> This patch adds xilinx CAN controller support.
> This driver supports both ZYNQ CANPS and Soft IP
> AXI CAN controller.
> 
> Signed-off-by: Kedareswara rao Appana <appanad@...inx.com>
> ---
> Changes for v7:
> - Updated the driver with review comments.
> - Moved the driver bindings doc as a separte patch.
> Changes for v6:
> - Updated the driver with review comments.
> - Used the clock names specified in the data sheet.
> - Updated the devicetree bindings doc as per Rob suggestion.
> Changes for v5:
> - Updated the driver with the review comments.
> - Remove the check for the tx fifo full interrupt condition
>   form Tx interrupt routine as we are checking it in the _xmit
>   routine.
> - Clearing the txok interrupt in the tx interrupt routine for
>   every Tx can frame.
> Changes for v4:
> - Added check for the tx fifo full interrupt condition in
> Tx interrupt routine.
> - Added be iohelper functions.
> - Moved the clock enable/disable to probe/remove because of
>   Added big endian support for AXI CAN controller case(reading
>   a register during probe for that we need to enable clock).
> Changes for v3:
> - Updated the driver with the review comments.
> - Modified the tranmit logic as per Marc suggestion.
> - Enabling the clock when the interface is up to reduce the
>   Power consumption.
> Changes for v2:
> - Updated with the review comments.
> - Removed the unnecessary debug prints.
> - include tx,rx fifo depths in ZYNQ CANPS case also
> ---
>  drivers/net/can/Kconfig      |    7 +
>  drivers/net/can/Makefile     |    1 +
>  drivers/net/can/xilinx_can.c | 1176 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 1184 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/net/can/xilinx_can.c

Mark: Any update on this one?
BTW: When you apply these patches you should apply 2/2 before 1/2. There is
new checking for binding.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform



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