netdev - [PATCH] cxgb4: Decode PCIe Gen3 link speed

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Date:	Mon, 28 Apr 2014 17:36:20 -0700
From:	Roland Dreier <roland@...nel.org>
To:	Dimitris Michailidis <dm@...lsio.com>
Cc:	"David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
	Roland Dreier <roland@...estorage.com>
Subject: [PATCH] cxgb4: Decode PCIe Gen3 link speed

From: Roland Dreier <roland@...estorage.com>

Add handling for " 8 GT/s" in print_port_info().

Signed-off-by: Roland Dreier <roland@...estorage.com>
---
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 6fe58913403a..24e16e3301e0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -5870,6 +5870,8 @@ static void print_port_info(const struct net_device *dev)
 		spd = " 2.5 GT/s";
 	else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
 		spd = " 5 GT/s";
+	else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
+		spd = " 8 GT/s";
 
 	if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
 		bufp += sprintf(bufp, "100/");
-- 
1.9.1

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