netdev - Re: [PATCH v2 1/2] Documentation: add Device tree bindings for Hisilicon hix5hd2 ethernet

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Message-ID: <53857714.3070603@linaro.org>
Date:	Wed, 28 May 2014 13:41:40 +0800
From:	zhangfei <zhangfei.gao@...aro.org>
To:	Mark Rutland <mark.rutland@....com>
CC:	"davem@...emloft.net" <davem@...emloft.net>,
	"arnd@...db.de" <arnd@...db.de>,
	"f.fainelli@...il.com" <f.fainelli@...il.com>,
	"sergei.shtylyov@...entembedded.com" 
	<sergei.shtylyov@...entembedded.com>,
	"David.Laight@...LAB.COM" <David.Laight@...LAB.COM>,
	"eric.dumazet@...il.com" <eric.dumazet@...il.com>,
	"haifeng.yan@...aro.org" <haifeng.yan@...aro.org>,
	"jchxue@...il.com" <jchxue@...il.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] Documentation: add Device tree bindings for Hisilicon
 hix5hd2 ethernet

Dear Mark

On 05/27/2014 09:34 PM, Mark Rutland wrote:
> On Tue, May 27, 2014 at 01:44:26PM +0100, Zhangfei Gao wrote:
>> Signed-off-by: Zhangfei Gao <zhangfei.gao@...aro.org>
>> ---
>>   .../bindings/net/hisilicon-hix5hd2-gmac.txt        |   36 ++++++++++++++++++++
>>   1 file changed, 36 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>>
>> diff --git a/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> new file mode 100644
>> index 0000000..5fe3835
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/hisilicon-hix5hd2-gmac.txt
>> @@ -0,0 +1,36 @@
>> +Hisilicon hix5hd2 gmac controller
>
> Just to clarify, is the SoC name "hix5hd2", or is the 'x' a wildcard?
"hix5hd2" is Soc name, which contains a series of similar chips.
>
>> +
>> +Required properties:
>> +- compatible: should be "hisilicon,hix5hd2-gmac".
>> +- reg: specifies base physical address(s) and size of the device registers.
>> +  The first region is the MAC register base and size.
>> +  The second region is external interface control register.
>
> Single registers? Are these not part of a larger block?
It is a single register, outside of the memory region.
gmac0: reg = <0xf9840000 0x1000>,<0xf984300c 0x4>;
gmac1: reg = <0xf9841000 0x1000>,<0xf9843010 0x4>;

The register is controlling interface mode, duplex etc.
In fact it is rather a bug fix to the silicon, when it is added with 
intension of not touching the original ip design.

It may be moved to the memory region in the future silicon design.
However, currently without such register, it can not work.

>
>> +- interrupts: should contain the MAC interrupts
>
> How many, in which order?
There is only one interrrupt.
How about:
- interrupts: interrupt for the device

>
>> +- #address-cells: must be <1>.
>> +- #size-cells: must be <0>.
>> +- phy-mode: see ethernet.txt [1].
>> +- phy-handle: see ethernet.txt [1].
>> +- mac-address: see ethernet.txt [1].
>> +- clocks: clock phandle and specifier pair.
>
> Is this the only clock input to the gmac block?
>
> Is the clock input named in any documentation?

We have abstract only ONE mac clock input, which is in other patch for 
drivers/clk/hisilicon/clk-hix5hd2.c
The clock input name is in include/dt-bindings/clock/hix5hd2-clock.h, 
described in "Documentation/devicetree/bindings/clock/hix5hd2-clock.txt"

How about:
- clocks: a pointer to the reference clock for this device.

Or should I mention hix5hd2-clock.h in this binding?

>
> Cheers,
> Mark.
>
>> +
>> +- PHY subnode: inherits from phy binding [2]
>> +
>> +[1] Documentation/devicetree/bindings/net/ethernet.txt
>> +[2] Documentation/devicetree/bindings/net/phy.txt
>> +
>> +Example:
>> +	gmac0: ethernet@...40000 {
>> +		compatible = "hisilicon,hix5hd2-gmac";
>> +		reg = <0xf9840000 0x1000>,<0xf984300c 0x4>;
>> +		interrupts = <0 71 4>;
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		phy-mode = "mii";
>> +		phy-handle = <&phy2>;
>> +		mac-address = [00 00 00 00 00 00];
>> +		clocks = <&clock HIX5HD2_MAC0_CLK>;
>> +
>> +		phy2: ethernet-phy@2 {
>> +			reg = <2>;
>> +		};
>> +	};
>> --
>> 1.7.9.5
>>
>>
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