netdev - RE: [PATCH v1 6/6] net: fec: Add software TSO support

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Date:	Fri, 30 May 2014 09:21:38 -0700
From:	Eric Dumazet <eric.dumazet@...il.com>
To:	"fugang.duan@...escale.com" <fugang.duan@...escale.com>
Cc:	"Frank.Li@...escale.com" <Frank.Li@...escale.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"ezequiel.garcia@...e-electrons.com" 
	<ezequiel.garcia@...e-electrons.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"shawn.guo@...aro.org" <shawn.guo@...aro.org>,
	"bhutchings@...arflare.com" <bhutchings@...arflare.com>,
	"stephen@...workplumber.org" <stephen@...workplumber.org>
Subject: RE: [PATCH v1 6/6] net: fec: Add software TSO support

On Fri, 2014-05-30 at 07:16 +0000, fugang.duan@...escale.com wrote:

> Yes, test found it bounce all TX frames.
> Use 2 descriptors to transfer one part, which bring more complicate for driver. Of course, 
> Performance must be better.
> 

How cpu handles misaligned 32bit accesses ?

> Digression information:
> Imx6dl FEC HW have bandwidth issue limit to 400 ~ 700Mbps. Current performance with TSO is 506Mbps, cpu loading is about 40%.
> Later chips with FEC IP support byte alignment, such as imx6sx. On imx6sx FEC, no SW TSO, tx bandwidth is 840~870Mbps, cpu loading is 100%,
> After the software TSO, tx bandwidth is 840Mbps, cpu loading is 48%.

Since you have some cpu cycles, have you tried to always use the bounce
thing, using one descriptor per MSS, instead of two ?

(headers + payload)

This might help to get better bandwidth, by lowering overhead on DMA and
on NIC.



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