netdev - Re: [PATCH v2] sh_eth: use RNC mode for R8A7790/R87791

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Message-Id: <20140602.140504.1151986761253502538.davem@davemloft.net>
Date:	Mon, 02 Jun 2014 14:05:04 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	sergei.shtylyov@...entembedded.com
Cc:	ben.dooks@...ethink.co.uk, linux-kernel@...ethink.co.uk,
	netdev@...r.kernel.org, nobuhiro.iwamatsu.yj@...esas.com,
	magnus.damn@...nsource.se, horms@...ge.net.au,
	yoshihiro.shimoda.uh@...esas.com, cm-hiep@...so.co.jp
Subject: Re: [PATCH v2] sh_eth: use RNC mode for R8A7790/R87791

From: Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
Date: Tue, 03 Jun 2014 00:55:38 +0400

> On 06/03/2014 12:49 AM, David Miller wrote:
> 
>>>     Looks like the early SH2/3 SoCs didn't implement the whole register.
>>> Despite that, sh_eth_dev_init() always writes to this register... :-/
>>> So far, the RMCR.RNC bit was mostly set for the Gigabit-capable
>>> controllers, however that rule wasn't strictly followed. Well, this
>>> driver is still a mess, and it's hard to deal with it without the
>>> necessary documentation.
> 
>> Why don't we therefore:
> 
>> 1) Skip the register write if the per-chip value is zero.
> 
>    I rather thought about not writing when the register is not
>    implemented.
> I'll probably look into this when I have time.
> 
>> 2) Add the RNC bit to all of the gigabit capable controllers.
> 
>    I probably misspoke -- all the Gigabit controllers already have it
>    set, it's just that some 100 MBbps ones have it set, but most don't.

So these chips that do not implement the register, they only process
one RX descriptor at a time until the interrupt handler re-enables
DMA receive?
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