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Date: Mon, 23 Jun 2014 09:18:42 +0000 From: David Laight <David.Laight@...LAB.COM> To: 'Chema Gonzalez' <chema@...gle.com>, Alexei Starovoitov <ast@...mgrid.com> CC: Daniel Borkmann <dborkman@...hat.com>, "David S. Miller" <davem@...emloft.net>, Ingo Molnar <mingo@...nel.org>, Steven Rostedt <rostedt@...dmis.org>, Eric Dumazet <edumazet@...gle.com>, Peter Zijlstra <a.p.zijlstra@...llo.nl>, Arnaldo Carvalho de Melo <acme@...radead.org>, "Jiri Olsa" <jolsa@...hat.com>, Thomas Gleixner <tglx@...utronix.de>, "H. Peter Anvin" <hpa@...or.com>, Andrew Morton <akpm@...ux-foundation.org>, Kees Cook <keescook@...omium.org>, Network Development <netdev@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org> Subject: RE: [PATCH v2 net-next 0/2] split BPF out of core networking From: Chema Gonzalez ... > 4.5. BPF_ST|BPF_MEM > Operation: *(size *) (dst_reg + off16) = imm32 > > This insn encodes 2 immediate values (the offset and the imm32 value) > in the insn, and actually forces the sock_filter_int 64-bit struct to > have both a 16-bit offset field and a 32-bit immediate field). In > fact, it's the only instructions that uses .off and .imm at the same > time (for all other instructions, at least one of the fields is always > 0). > > This did not exist in classic BPF (where BPF_ST|BPF_MEM actually did > "mem[pc->k] = A;"). In fact, it's rare to find an ISA that allows > encoding 2 immediate values in a single insn. My impression (after > checking the x86 JIT implementation, which works on the eBPF code) is > that this was added as an x86 optimization, because x86 allows > encoding 2 values (offset and immediate) by using the displacement and > immediate suffixes. I wonder whether the ISA would be more readable if > we did this in 2 insn, one to put dst_reg+off16 in a temporary > register, and the second a simpler BPF_STX|BPF_MEM. Then we could use > the same space for the immediate and offset fields. One option is to add code to the x86 JIT to detect the two instruction sequence and generate a single instruction. Thinks further, the JIT might be easier to write if there is a temporary register that is defined to be only valid for the next instruction (or two). Then the JIT can completely optimise away any assignments to it without requiring a full analysis of the entire program. David
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