netdev - RE: [PATCH] net: can: Remodel FlexCAN register read/write APIs for BE instances

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Message-ID: <063D6719AE5E284EB5DD2968C1650D6D17264A8E@AcuExch.aculab.com>
Date:	Wed, 25 Jun 2014 08:58:29 +0000
From:	David Laight <David.Laight@...LAB.COM>
To:	'Bhupesh Sharma' <bhupesh.sharma@...escale.com>,
	"mkl@...gutronix.de" <mkl@...gutronix.de>,
	"linux-can@...r.kernel.org" <linux-can@...r.kernel.org>
CC:	"wg@...ndegger.com" <wg@...ndegger.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH] net: can: Remodel FlexCAN register read/write APIs for
 BE instances

From: Bhupesh Sharma
> The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is
> modelled in a big-endian fashion, i.e. the registers and the
> message buffers are organized in a BE way.
> 
> More details about the LS1021A SoC can be seen here:
> http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1021A&nodeId=018rH325E4017B#
> 
> This patch ensures that the register read/write APIs are remodelled
> to address such cases, while ensuring that existing platforms (where
> the FlexCAN IP was modelled in LE way) do not break.
...
Munged to the new code....
> +static inline u32 flexcan_read(const struct flexcan_priv *priv,
> +			       void __iomem *addr)
>  {
> +	if (priv->devtype_data->module_is_big_endian)
> +		return ioread32be(addr);
> +	else
> +		return ioread32(addr);
>  }
> 
> +static inline void flexcan_write(const struct flexcan_priv *priv,
> +				 u32 val, void __iomem *addr)
>  {
> +	if (priv->devtype_data->module_is_big_endian)
> +		iowrite32be(val, addr);
> +	else
> +		iowrite32(val, addr);
>  }

Hmmm....
If performance ever matters that is horrid.
Probably to the point where making the functions 'inline' is just code bloat.

	David



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