netdev - Re: [net] igb: Workaround for i210 Errata 25: Slow System Clock

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Date:	Thu, 10 Jul 2014 01:48:41 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	jeffrey.t.kirsher@...el.com
Cc:	todd.fujinaka@...el.com, netdev@...r.kernel.org,
	nhorman@...hat.com, sassmann@...hat.com, stable@...r.kernel.org
Subject: Re: [net] igb: Workaround for i210 Errata 25: Slow System Clock

From: Jeff Kirsher <jeffrey.t.kirsher@...el.com>
Date: Thu, 10 Jul 2014 01:47:15 -0700

> From: Todd Fujinaka <todd.fujinaka@...el.com>
> 
> On some devices, the internal PLL circuit occasionally provides the
> wrong clock frequency after power up. The probability of failure is less
> than one failure per 1000 power cycles. When the failure occurs, the
> internal clock frequency is around 1/20 of the correct frequency.
> 
> Cc: stable <stable@...r.kernel.org>
> Signed-off-by: Todd Fujinaka <todd.fujinaka@...el.com>
> Tested-by: Aaron Brown <aaron.f.brown@...el.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@...el.com>

Applied, thanks Jeff.
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