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Date:	Fri, 10 Oct 2014 16:30:50 +0000
From:	David Laight <David.Laight@...LAB.COM>
To:	'Eric Dumazet' <eric.dumazet@...il.com>
CC:	"'alexander.h.duyck@...hat.com'" <alexander.h.duyck@...hat.com>,
	"David Miller" <davem@...emloft.net>,
	"alexander.duyck@...il.com" <alexander.duyck@...il.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH] flow-dissector: Fix alignment issue in
 __skb_flow_get_ports

From: Eric Dumazet [mailto:eric.dumazet@...il.com]
> Sent: 10 October 2014 16:34
> To: David Laight
> Cc: 'alexander.h.duyck@...hat.com'; David Miller; alexander.duyck@...il.com; netdev@...r.kernel.org
> Subject: Re: [PATCH] flow-dissector: Fix alignment issue in __skb_flow_get_ports
> 
> On Fri, 2014-10-10 at 14:57 +0000, David Laight wrote:
> 
> > I think there is code to copy the IP and TCP headers to aligned memory
> > before they are parsed.
> 
> There is no such thing. You are here on netdev list, please read the
> code before doing such claims.

I did say 'I think'...
I must be thinking of some similar code somewhere else.
Possibly just the code that ensures the header isn't fragmented.

> > > The problem is the igb / ixgbe / fm10k hardware doesn't have a means of
> > > inserting padding from its side...
> >
> > Shoot the hardware engineers.
> >
> > You aren't going to get the performance you expect from a 10Ge card
> > unless the rx buffers are 'correctly' aligned.
> 
> That is simply not true on current x86 cpus. They simply dont care at
> all.

I was referring to using them on sparc64, not x86.

I know that current intel x86 cpu have support for misaligned 'rep movsd',
but I thought there was still a small cost (maybe one clock) for
single word transfers.
So maybe they care 'just a little bit'.

> You cannot blame Intel for other arches.

True, but this does mean that you don't really want to use these adapters
on a system that can't to unaligned accesses.

	David

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