netdev - RE: [PATCH] net: fec: ptp: fix convergence issue to support LinuxPTP stack

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Message-ID: <dd389a4bba714e3b9068c93e44f8385f@BLUPR03MB373.namprd03.prod.outlook.com>
Date:	Wed, 15 Oct 2014 01:28:31 +0000
From:	"fugang.duan@...escale.com" <fugang.duan@...escale.com>
To:	Richard Cochran <richardcochran@...il.com>,
	"Frank.Li@...escale.com" <Frank.Li@...escale.com>
CC:	David Miller <davem@...emloft.net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"bhutchings@...arflare.com" <bhutchings@...arflare.com>
Subject: RE: [PATCH] net: fec: ptp: fix convergence issue to support LinuxPTP
 stack

From: Richard Cochran <richardcochran@...il.com> Sent: Wednesday, October 15, 2014 2:50 AM
>To: Li Frank-B20596
>Cc: David Miller; Duan Fugang-B38611; netdev@...r.kernel.org;
>bhutchings@...arflare.com
>Subject: Re: [PATCH] net: fec: ptp: fix convergence issue to support
>LinuxPTP stack
>
>On Tue, Oct 14, 2014 at 06:43:51PM +0000, Frank.Li@...escale.com wrote:
>> Only MX6 SX. Only MX6 SX added FEC_QUIRK_BUG_CAPTURE.
>
>But what about this comment:
>
>+/* ENET Block Guide/ Chapter for the iMX6SLX (PELE) address one issue:
>+ * Incorrect behavior for ENET_ATCR[Capture and Restart Bits]. These
>+bits will
>+ * always read a value zero. When these bits are set to 1'b1, these
>+should hold
>+ * value 1'b1 until the counter value is capture in the register clock
>domain.
>+ */
>
>It sounds like the bits are "sticky" until the counter value has been
>latched. Therefore you need to check the bits before reading the counter,
>but the code does not do this for the case of !SX.
>
>Thanks,
>Richard


Hi, Richard,

Fristly, the patch just fix ptp issue for imx6sx.
Secondly, pls see the patch commit log:

    IEEE 1588 module has one hw issue in capturing the ATVR register. According
    to the user manual it is:
               ENET0->ATCR |= ENET_ATCR_CAPTURE_MASK;
               while(ENET0->ATCR & ENET_ATCR_CAPTURE_MASK);
               ts_counter_ns = ENET0->ATVR;
    Incorrect behavior for ENET_ATCR[Capture and Restart Bits]. These bits will always
    read a value zero. According to SPEC, when these bits are set to 1'b1, these should
    hold value 1'b1 until the counter value is capture in the register clock domain.
    
    Unfortunately there is a bug with the way the bit "ENET_ATCR_CAPTURE" clears.
    So need something like:
               ENET0->ATCR |= ENET_ATCR_CAPTURE_MASK;
               wait();
               ts_counter_ns = ENET0->ATVR;
    
    The wait-time to be at least 6 clock cycle of the slower clock between the register
    clock and the 1588 clock. The 1588 ts_clk is 25Mhz, register clock is 66Mhz, so the
    wait-time must be greater than 240ns (40ns * 6). The workaround is that adding 1us
    delay before read ATVR.



There need add delay instead of while().

Thanks,
Andy
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