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Message-ID: <1415193393-30023-3-git-send-email-b29396@freescale.com>
Date: Wed, 5 Nov 2014 21:16:33 +0800
From: Dong Aisheng <b29396@...escale.com>
To: <linux-can@...r.kernel.org>
CC: <mkl@...gutronix.de>, <wg@...ndegger.com>,
<varkabhadram@...il.com>, <netdev@...r.kernel.org>,
<socketcan@...tkopp.net>, <b29396@...escale.com>,
<linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH V3 3/3] can: m_can: workaround for transmit data less than 4 bytes
At least on the i.MX6SX TO1.2 with M_CAN IP version 3.0.1, an issue with
the Message RAM was discovered. Sending CAN frames with dlc less
than 4 bytes will lead to bit errors, when the first 8 bytes of
the Message RAM have not been initialized (i.e. written to).
To work around this issue, the first 8 bytes are initialized in open()
function.
Without the workaround, we can easily see the following errors:
root@...6qdlsolo:~# ip link set can0 up type can bitrate 1000000
[ 66.882520] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
root@...6qdlsolo:~# cansend can0 123#112233
[ 66.935640] m_can 20e8000.can can0: Bit Error Uncorrected
Signed-off-by: Dong Aisheng <b29396@...escale.com>
---
ChangeLog
v2->v3:
* add i.MX chip version in issue in commit message
v1->v2:
* initialize the first 8 bytes of Tx Buffer of Message RAM in open()
to workaround the issue
---
drivers/net/can/m_can/m_can.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
index eee1533..567cd27 100644
--- a/drivers/net/can/m_can/m_can.c
+++ b/drivers/net/can/m_can/m_can.c
@@ -905,6 +905,16 @@ static void m_can_chip_config(struct net_device *dev)
/* set bittiming params */
m_can_set_bittiming(dev);
+ /* At least on the i.MX6SX TO1.2 with M_CAN IP version 3.0.1,
+ * (CREL = 30130506) an issue with the Message RAM was discovered.
+ * Sending CAN frames with dlc less than 4 bytes will lead to bit
+ * errors, when the first 8 bytes of the Message RAM have not been
+ * initialized (i.e. written to). To work around this issue, the
+ * first 8 bytes are initialized here.
+ */
+ m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(0), 0x0);
+ m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(1), 0x0);
+
m_can_config_endisable(priv, false);
}
--
1.9.1
--
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