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Date:	Thu, 13 Nov 2014 14:38:19 -0500 (EST)
From:	David Miller <davem@...emloft.net>
To:	al.kochet@...il.com
Cc:	netdev@...r.kernel.org, steve.glendinning@...well.net
Subject: Re: [PATCH 2/2] net/smsc911x: Fix delays in the PHY enable/disable
 routines

From: Alexander Kochetkov <al.kochet@...il.com>
Date: Thu, 13 Nov 2014 05:26:20 +0400

> Increased delay in the smsc911x_phy_disable_energy_detect (from 1ms to 2ms).
> Dropped delays in the smsc911x_phy_enable_energy_detect (100ms and 1ms).
> 
> The patch affect SMSC LAN generation 4 chips with integrated PHY (LAN9221).
> 
> I saw problems with soft reset due to wrong udelay timings.
> After I fixed udelay, I measured the time needed to bring integrated PHY
> from power-down to operational mode (the time beetween clearing EDPWRDOWN
> bit and soft reset complete event). I got 1ms (measured using ktime_get).
> The value is equal to the current value (1ms) used in the
> smsc911x_phy_disable_energy_detect. It is near the upper bound and in order
> to avoid rare soft reset faults it is doubled (2ms).
> 
> I don't know official timing for bringing up integrated PHY as specs doesn't
> clarify this (or may be I didn't found).
> 
> It looks safe to drop delays before and after setting EDPWRDOWN bit
> (enable PHY power-down mode). I didn't saw any regressions with the patch.
> 
> The patch was reviewed by Steve Glendinning and Microchip Team.
> 
> Signed-off-by: Alexander Kochetkov <al.kochet@...il.com>
> Acked-by: Steve Glendinning <steve.glendinning@...well.net>

Applied.
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