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Message-ID: <546648A8.1000102@ti.com>
Date: Fri, 14 Nov 2014 23:53:36 +0530
From: Mugunthan V N <mugunthanvnm@...com>
To: John Ogness <john.ogness@...utronix.de>,
<linux-kernel@...r.kernel.org>
CC: <davem@...emloft.net>, <balbi@...com>, <george.cherian@...com>,
<jhovold@...il.com>, <mpa@...gutronix.de>,
<bhutchings@...arflare.com>, <zonque@...il.com>,
<tklauser@...tanz.ch>, <netdev@...r.kernel.org>
Subject: Re: [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset
On Friday 14 November 2014 08:12 PM, John Ogness wrote:
> The TX_IN_SEL offset for the CPSW_PORT/TX_IN_CTL register was
> incorrect. This caused the Dual MAC mode to never get set when
> it should. It also caused possible unintentional setting of a
> bit in the CPSW_PORT/TX_BLKS_REM register.
>
> The purpose of setting the Dual MAC mode for this register is to:
>
> "... allow packets from both ethernet ports to be written into
> the FIFO without one port starving the other port."
> - AM335x ARM TRM
>
> Signed-off-by: John Ogness <john.ogness@...utronix.de>
Reviewed-by: Mugunthan V N <mugunthanvnm@...com>
Regards
Mugunthan V N
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