netdev - RE: [net-next 03/12] i40e: Handle a single mss packet with more than 8 frags

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:	Tue, 18 Nov 2014 09:46:58 +0000
From:	David Laight <David.Laight@...LAB.COM>
To:	'Eric Dumazet' <eric.dumazet@...il.com>
CC:	"'Nelson, Shannon'" <shannon.nelson@...el.com>,
	"Kirsher, Jeffrey T" <jeffrey.t.kirsher@...el.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"Kong, Serey" <serey.kong@...el.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"nhorman@...hat.com" <nhorman@...hat.com>,
	"sassmann@...hat.com" <sassmann@...hat.com>,
	"jogreene@...hat.com" <jogreene@...hat.com>
Subject: RE: [net-next 03/12] i40e: Handle a single mss packet with more
 than 8 frags

From: Eric Dumazet
> On Mon, 2014-11-17 at 16:16 +0000, David Laight wrote:
> 
> > Except that a TSO packet is likely to be just under 64k and comprise of
> > a small header and 16 other fragments - most of which will be a complete 4k page.
> >
> 
> This is the section of the code sending a _non_ TSO packet.

That isn't entirely clear from the patch context.

For a non-TSO packet the skb_serialize() is less likely to fail
since it doesn't need contiguous pages.
(Unless you are sending 9k jumbo frames).

Actually many of the older ethernet devices will suffer buffer underrun
if given too many small fragments due to lack of bus bandwidth.
The high latencies of PCIe will make that worse - especially at high speeds.

Presumably these devices use 'store and forward' when doing TSO (or
maybe even when just adding a checksum) removing any real problems
caused by PCIe latency?

	David