netdev - Re: Device Tree Binding for Marvell DSA Switch on imx28 board over Mdio Interface

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Date:	Tue, 18 Nov 2014 10:23:14 -0800
From:	Florian Fainelli <f.fainelli@...il.com>
To:	Oliver Graute <oliver.graute@...il.com>,
	Andrew Lunn <andrew@...n.ch>
CC:	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	buytenh@...tstofly.org
Subject: Re: Device Tree Binding for Marvell DSA Switch on imx28 board over
 Mdio Interface

On 11/18/2014 12:30 AM, Oliver Graute wrote:
>> Hi Oliver
>>
>> How do you have the strapping pins on the switch set? They determine
>> what address on the mdio bus the chip responds to.
> 
> On the circuit diagram the PIN 54  (P5_IND1/P5ID1) is set to
> "Configuration Address: 0101"
> P5_MODE[3:0]=0111 = Single RMII MAC Mode (100Mbps FD with 50 MHz clock input)
> PIN 59 R1_LED/NO_CPU Configuration: CPU is attached SMI address is 0x10 to 0x1F
> 
> But what is the mdio address of the whole switch? or can I only
> address individual phy ports?

You should specify in the Device Tree the switch pseudo-PHY address,
typically 16 for Marvell switches. You can still access the individual
ports' PHY addresses using address 0 through N.

> 
> The Port 5 Pins of the  Marvell 88e6071 switch are connected via RMII
> to a Micrel Phy KSZ8051. And this Micrel Phy is connected to the MAC
> of IMX28 CPU (also RMII).
> 
>> Does your u-boot have commands to read arbitrary phy registers?
>> Generally, reading a register that does not exist gives 0xffff.  So
>> try some reads at different addresses and see what you can find.
> 
> I can read phy registers from the Marvell switch by a Tool called
> mii_demo it is a bit like mii_diag. It can read PHY registers from the
> switch Ports via IOCTL.
> This is working via some undefined ioctl SIOCSMIIREG2, SIOCGMIIPHY2.
> 
> 
> Example:
> #read SMI PHY Command Register 18 from Switch with IEEE 802.3 Clause 22
> mii_demo -rd eth0 23 0x18
> 
> 0x1680
> 
> Best regards,
> 
> Oliver
> 

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