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Message-ID: <CAMuHMdUyJk+27BsGaZGh+TOqhA5qH4q_pL2hM=tp-Ktn=hkFnw@mail.gmail.com>
Date: Wed, 7 Jan 2015 09:42:22 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@...esas.com>
Cc: "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Linux-sh list <linux-sh@...r.kernel.org>
Subject: Re: [PATCH] sh_eth: Fix access to TRSCER register
Hi Iwamatsu-san,
On Wed, Jan 7, 2015 at 6:35 AM, Nobuhiro Iwamatsu
<nobuhiro.iwamatsu.yj@...esas.com> wrote:
> TRSCER register is configured differently by SoCs. TRSCER of R-Car is
> RINT8 bit only valid, other bits are reserved bits.
> This removes access to TRSCER register reserve bit.
>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@...esas.com>
> ---
> drivers/net/ethernet/renesas/sh_eth.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
> index c29ba80..59ee457 100644
> --- a/drivers/net/ethernet/renesas/sh_eth.c
> +++ b/drivers/net/ethernet/renesas/sh_eth.c
> @@ -1294,7 +1294,11 @@ static int sh_eth_dev_init(struct net_device *ndev, bool start)
> /* Frame recv control (enable multiple-packets per rx irq) */
> sh_eth_write(ndev, RMCR_RNC, RMCR);
>
> - sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER);
> + if (mdp->cd->register_type == SH_ETH_REG_FAST_RCAR)
This catches both the R-Car Gen1 and R-Car Gen2 cases.
According to the datasheets, r8a7778/9 do have the other bits?
Only R-Car Gen2 doesn't have them.
> + sh_eth_write(ndev, DESC_I_RINT8, TRSCER);
> + else
> + sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2,
> + TRSCER);
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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