netdev - Re: [PATCH net] cxgb4: Fix PCI-E Memory window interface for big-endian systems

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Message-Id: <20150227.155911.683029385758928369.davem@davemloft.net>
Date:	Fri, 27 Feb 2015 15:59:11 -0500 (EST)
From:	David Miller <davem@...emloft.net>
To:	hariprasad@...lsio.com
Cc:	netdev@...r.kernel.org, leedom@...lsio.com, anish@...lsio.com,
	nirranjan@...lsio.com, kumaras@...lsio.com
Subject: Re: [PATCH net] cxgb4: Fix PCI-E Memory window interface for
 big-endian systems

From: Hariprasad Shenai <hariprasad@...lsio.com>
Date: Wed, 25 Feb 2015 16:50:04 +0530

> When doing reads and writes to adapter memory via the PCI-E Memory Window
> interface, data gets swizzled on 4-byte boundaries on Big-Endian systems
> because we need to account for the register read/write interface which
> incorporates a swizzle onto the Little-Endian PCI-E Bus.
> 
> Based on original work by Casey Leedom <leedom@...lsio.com>
> 
> Signed-off-by: Hariprasad Shenai <hariprasad@...lsio.com>

Applied.
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