Date:	Thu, 09 Apr 2015 13:26:00 -0700
From:	Florian Fainelli <f.fainelli@...il.com>
To:	Mason <slash.tmp@...e.fr>, netdev@...r.kernel.org
CC:	Daniel Mack <daniel@...que.org>, Mugunthan <mugunthanvnm@...com>,
	"David S. Miller" <davem@...emloft.net>,
	Matus Ujhelyi <ujhelyi.m@...il.com>
Subject: Re: Atheros 8035 PHY only works when at803x_config_init() is commented
 out

On 09/04/15 12:30, Mason wrote:
> Florian Fainelli wrote:
>> Mason wrote:
>>> Florian Fainelli wrote:
>>>
>>>> Mason wrote:
>>>>
>>>>> Is speed auto-negotiation supposed to be complete when phy_init_hw exits?
>>>>
>>>> There is no such guarantee, and the PHY state machine is started later,
>>>> which will take care of auto-neg and other things.
>>>
>>> That's what I thought.
>>>
>>> So it's expected that many status bits will only change later.
>>>
>>> You didn't comment on my patch. What's your take on it?
>>
>> Quoting IEEE 802.3 section 2, paragraph 22.2.4.1:
>>
>> "Resetting a PHY is accomplished by setting bit 0.15 to a logic one.
>> This action shall set the status and control registers to their 
>> default states. As a consequence this action may change the internal 
>> state of the PHY and the state of the physical link associated with 
>> the PHY. This bit is self-clearing, and a PHY shall return a value
>> of one in bit 0.15 until the reset process is completed. A PHY is
>> not required to accept a write transaction to the control register 
>> until the reset process is completed, and writes to bits of the 
>> control register other than 0.15 may have no effect until the reset 
>> process is completed. The reset process shall be completed within
>> 0.5 s from the setting of bit 0.15"
>>
>> So even though this is not extremely specific about whether or not doing
>> a RMW instead of W is accepted, considering that this resets the PHY
>> internal state, and the fact that there is a lack of clarify on whether
>> setting any bits other than 15 is going to fall under the "A PHY is not
>> required to accept a write transaction to the control register until the
>> reset process is completed" statement, setting only this bit at least
>> guarantees that you are back into your reset defaults.
>>
>> As Daniel suggested, I would be looking for undocumented/proprietary
>> registers for reasons as to why your PHY is not working, in particular
>> (RG)MII tuning.
> 
> Am I the only having problems with the AR8035? :-(
> 
> The standard driver works for everyone but me? 
> 
> Did you take a look at the data sheet? Do you understand the
> difference between "Hardware Reset" and "Software Reset"?

I did not.

> 
> Maybe on my PHY, writing BMCR_RESET to BMCR triggers a SW reset,
> while it triggers a HW reset on other boards?
> 
> Would that be possible?

Possible, but certainly non-compliant behavior, in which case you would
want to override the soft_reset() callback.

> 
> Also, why do you say the PHY is not working? When I apply the
> patch I proposed, it doesn't malfunction.

There are no BMCR registers that would affect directly the passing of
unicast or broadcast traffic with distinction, which is how you
originally reported the problem, or maybe that was a bad description of
the issue?

Have you checked the Ethernet MAC MIB counters to see if there are any
errors reported differently from the working case to the non-working
case? What about your link partner, what does it looks like on its end
when it does not work?
-- 
Florian
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