netdev - Re: Atheros 8035 PHY only works when at803x_config

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Message-ID: <5527E67F.7010107@free.fr>
Date:	Fri, 10 Apr 2015 17:04:31 +0200
From:	Mason <slash.tmp@...e.fr>
To:	Fabio Estevam <festevam@...il.com>
CC:	Florian Fainelli <f.fainelli@...il.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	Daniel Mack <daniel@...que.org>,
	Mugunthan <mugunthanvnm@...com>,
	"David S. Miller" <davem@...emloft.net>,
	Matus Ujhelyi <ujhelyi.m@...il.com>
Subject: Re: Atheros 8035 PHY only works when at803x_config_init() is
 commented out

Fabio Estevam wrote:
> Fabio Estevam wrote:
>> Mason wrote:
>>
>>> Am I the only having problems with the AR8035? :-(
>>>
>>> The standard driver works for everyone but me?
>>
>> Works well on a imx6q-hummingboard:
>>
>> fec 2188000.ethernet eth0: Freescale FEC PHY driver [Atheros 8035
>> ethernet] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)

Could you tell me the value of BMCR on entry and exit of phy_init_hw?

> Forgot to point out that we also have a 8035 fixup in
> arch/arm/mach-imx/mach-imx6q.c. Search for ar8035_phy_fixup().

Thanks for the pointer.

Freescale's ar8031_phy_fixup() is almost the same as U-boot's ar8035_config()
The only difference is one extra sanitizing instruction: val &= 0xffe3;

What's the point of masking bits 3 and 4, when they are set by the
next instruction:

   val &= 0xffe3;
   val |= 0x18;

The result of these two operations is
bit2=0 bit3=1 bit4=1 other=unchanged

Bit 2 is undocumented, why does Freescale set it to 0?

The tx clock delay is already done in the generic driver.
Do you know why it is necessary? Why not rx clock delay also?

I'll give the "disable SmartEEE" fixup a try.

Not sure why they reset the POWER_DOWN bit? It's cleared by both
HW and SW resets.

Regards.

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