netdev - Re: [GIT PULL] parisc architecture updates for v4.3

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Message-Id: <D6403D2F-339E-4986-ABED-26455A157F7A@alum.mit.edu>
Date:	Tue, 3 Nov 2015 15:43:06 -0800
From:	Guy Harris <guy@...m.mit.edu>
To:	Helge Deller <deller@....de>
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>,
	David Miller <davem@...emloft.net>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Parisc List <linux-parisc@...r.kernel.org>,
	James Bottomley <James.Bottomley@...senpartnership.com>,
	John David Anglin <dave.anglin@...l.net>,
	Network Development <netdev@...r.kernel.org>
Subject: Re: [GIT PULL] parisc architecture updates for v4.3


On Nov 3, 2015, at 3:03 PM, Helge Deller <deller@....de> wrote:

> Sadly it's nowhere clearly documented how big the L1 cacheline of parisc really is.

To which particular PA-RISC processor are you referring?  It might not be the same on all processors.

If openpa.net is to be believed, then:

The 7100LC has 32 byte cache lines on the off-chip cache:

	http://www.openpa.net/pa-risc_processor_pa-7100lc.html

and the 8500 has "32 or 64 Byte cache line size", which may be referring to the on-chip caches:

	http://www.openpa.net/pa-risc_processor_pa-8500.html--
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