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Date:	Sun, 22 Nov 2015 22:24:01 +0100
From:	Marcin Wojtas <mw@...ihalf.com>
To:	Arnd Bergmann <arnd@...db.de>
Cc:	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
	Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
	Andrew Lunn <andrew@...n.ch>,
	Russell King - ARM Linux <linux@....linux.org.uk>,
	Jason Cooper <jason@...edaemon.net>,
	Yair Mahalalel <myair@...vell.com>,
	Grzegorz Jaszczyk <jaz@...ihalf.com>,
	Simon Guinot <simon.guinot@...uanux.org>,
	Evan Wang <xswang@...vell.com>, nadavh@...vell.com,
	Lior Amsalem <alior@...vell.com>,
	Tomasz Nowicki <tn@...ihalf.com>,
	Gregory Clément 
	<gregory.clement@...e-electrons.com>, nitroshift@...oo.com,
	"David S. Miller" <davem@...emloft.net>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Subject: Re: [PATCH 07/13] bus: mvebu-mbus: provide api for obtaining IO and
 DRAM window information

Arnd,

2015-11-22 21:02 GMT+01:00 Arnd Bergmann <arnd@...db.de>:
> On Sunday 22 November 2015 08:53:53 Marcin Wojtas wrote:
>> This commit enables finding appropriate mbus window and obtaining its
>> target id and attribute for given physical address in two separate
>> routines, both for IO and DRAM windows. This functionality
>> is needed for Armada XP/38x Network Controller's Buffer Manager and
>> PnC configuration.
>>
>> Signed-off-by: Marcin Wojtas <mw@...ihalf.com>
>>
>> [DRAM window information reference in LKv3.10]
>> Signed-off-by: Evan Wang <xswang@...vell.com>
>>
>
> It's too long ago to remember all the details, but I thought we
> had designed this so the configuration can just be done by
> describing it in DT. What am I missing?
>

And those functions do not break this approach. They just enable
finding and reading the settings of MBUS windows done during initial
configuration. Please remember that mvebu-mbus driver fills the MBUS
windows registers basing on DT, however it just configures access CPU
- DRAM/perfipheral.

In this particular case only physical adresses of buffers are known
and we have to 'open windows' between BM <-> DRAM and NETA <-> BM
internal memory. Hence instead of hardcoding size/target/attribute, we
can take information stored in CPU DRAM/IO windows registers.

Best regards,
Marcin
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