netdev - Re: [PATCH] net: fec: fix enet

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Message-ID: <20151130075617.0f880cd1@ipc1.ka-ro>
Date:	Mon, 30 Nov 2015 07:56:17 +0100
From:	Lothar Waßmann <LW@...O-electronics.de>
To:	Duan Andy <fugang.duan@...escale.com>
Cc:	Andrew Lunn <andrew@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Fabio Estevam <Fabio.Estevam@...escale.com>,
	Kevin Hao <haokexin@...il.com>,
	Lucas Stach <l.stach@...gutronix.de>,
	Philippe Reynes <tremyfr@...il.com>,
	Russell King <rmk+kernel@....linux.org.uk>,
	Uwe Kleine-K?nig <u.kleine-koenig@...gutronix.de>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	Stefan Agner <stefan@...er.ch>
Subject: Re: [PATCH] net: fec: fix enet_out clock handling

Hi,

> From: Lothar Waßmann <LW@...O-electronics.de> Sent: Friday, November 27, 2015 9:39 PM
> > To: Andrew Lunn; David S. Miller; Estevam Fabio-R49496; Kevin Hao; Lothar
> > Waßmann; Lucas Stach; Duan Fugang-B38611; Philippe Reynes; Russell King;
> > Uwe Kleine-König; linux-kernel@...r.kernel.org; netdev@...r.kernel.org;
> > Stefan Agner
> > Subject: [PATCH] net: fec: fix enet_out clock handling
> > 
> > When ENET_OUT is being used as reference clock for an external PHY, the
> > clock must not be disabled while the PHY is active. Otherwise the PHY may
> > lose its internal state and require a reset to become functional again.
> > 
> > A symptom for this bug is a network interface that constantly toggles
> > between UP and DOWN state:
> > fec 800f0000.ethernet eth0: Link is Up - 100Mbps/Full - flow control
> > rx/tx fec 800f0000.ethernet eth0: Link is Down fec 800f0000.ethernet eth0:
> > Link is Up - 100Mbps/Full - flow control rx/tx fec 800f0000.ethernet eth0:
> > Link is Down [...]
> > 
> > Signed-off-by: Lothar Waßmann <LW@...O-electronics.de>
> > ---
> >  drivers/net/ethernet/freescale/fec_main.c | 34 +++++++++++++------------
> > ------
> >  1 file changed, 14 insertions(+), 20 deletions(-)
> > 
> 
> When MAC is not ready with clocks disabled,  it is not necessary to supply clock for PHY. In fact, PHY also is not ready, why does it need clock ?
> For your problem, you must add PHY reset in your dts file to resolve your problem.
> 
The phy-reset-gpio property is set in the DTB. But fec_reset_phy()
which asserts the RESET is only called from within the probe() function.
It should probably be called from fec_restart() instead?


Lothar Waßmann
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