netdev - [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

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Message-ID: <1449302088-53037-4-git-send-email-yankejian@huawei.com>
Date:	Sat, 5 Dec 2015 15:54:48 +0800
From:	yankejian <yankejian@...wei.com>
To:	<davem@...emloft.net>, <robh+dt@...nel.org>, <pawel.moll@....com>,
	<mark.rutland@....com>, <ijc+devicetree@...lion.org.uk>,
	<galak@...eaurora.org>, <xuwei5@...ilicon.com>,
	<catalin.marinas@....com>, <will.deacon@....com>,
	<wangkefeng.wang@...wei.com>, <dingtianhong@...wei.com>,
	<liguozhu@...wei.com>, <Yisen.Zhuang@...wei.com>,
	<sboyd@...eaurora.org>, <haojian.zhuang@...aro.org>,
	<wangzhou1@...ilicon.com>, <bintian.wang@...wei.com>,
	<long.wanglong@...wei.com>, <leo.yan@...aro.org>
CC:	<haifeng.wei@...wei.com>, <devicetree@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
	<linuxarm@...wei.com>
Subject: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board

This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.

Signed-off-by: yankejian <yankejian@...wei.com>
---
 .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
 		reg = <0xb0000000 0x10000>;
 	};
 
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+	/* for HiP05 PCIe-SAS system */
+	pcie_sas: system_controller@...0000000 {
+		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+		reg = <0xb0000000 0x10000>;
+	};
 -----------------------------------------------------------------------
 Hisilicon CPU controller
 
-- 
1.9.1

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