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Message-ID: <56658E36.40702@huawei.com>
Date:	Mon, 7 Dec 2015 21:48:38 +0800
From:	Bintian <bintian.wang@...wei.com>
To:	yankejian <yankejian@...wei.com>
CC:	Rob Herring <robh@...nel.org>, <davem@...emloft.net>,
	<pawel.moll@....com>, <mark.rutland@....com>,
	<ijc+devicetree@...lion.org.uk>, <galak@...eaurora.org>,
	<xuwei5@...ilicon.com>, <catalin.marinas@....com>,
	<will.deacon@....com>, <wangkefeng.wang@...wei.com>,
	<dingtianhong@...wei.com>, <liguozhu@...wei.com>,
	<Yisen.Zhuang@...wei.com>, <sboyd@...eaurora.org>,
	<haojian.zhuang@...aro.org>, <wangzhou1@...ilicon.com>,
	<long.wanglong@...wei.com>, <leo.yan@...aro.org>,
	<haifeng.wei@...wei.com>, <devicetree@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
	<linuxarm@...wei.com>
Subject: Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree
 bindings for Hisilicon D02 Board

On 2015/12/7 21:16, Rob Herring wrote:
> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>> This patch adds documentation for the devicetree bindings used by the
>> DT files of Hisilicon Hip05-D02 development board.
>>
>> Signed-off-by: yankejian <yankejian@...wei.com>
You may need to configure as  "Kejian Yan <yankejian@...wei.com>"     :)

BR,

Bintian
>> ---
>>   .../devicetree/bindings/arm/hisilicon/hisilicon.txt      | 16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> index 6ac7c00..5318d78 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> @@ -187,6 +187,22 @@ Example:
>>   		reg = <0xb0000000 0x10000>;
>>   	};
>>   
>> +Hisilicon HiP05 PERISUB system controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> This should be more specific and have the SOC name in it.
>
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> +	/* for HiP05 PCIe-SAS system */
>> +	pcie_sas: system_controller@...0000000 {
>> +		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> The example doesn't match.
>
>> +		reg = <0xb0000000 0x10000>;
>> +	};
>>   -----------------------------------------------------------------------
>>   Hisilicon CPU controller
>>   
>> -- 
>> 1.9.1
>>
>> --
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>


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