netdev - Re: [PATCH] net: emac: emac gigabit ethernet controller driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:	Thu, 31 Dec 2015 17:03:57 -0600
From:	Rob Herring <robh@...nel.org>
To:	Gilad Avidov <gavidov@...eaurora.org>
Cc:	Florian Fainelli <f.fainelli@...il.com>,
	netdev <netdev@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	linux-arm-msm <linux-arm-msm@...r.kernel.org>,
	Sagar Dharia <sdharia@...eaurora.org>, shankerd@...eaurora.org,
	Timur Tabi <timur@...eaurora.org>,
	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	vikrams@...eaurora.org
Subject: Re: [PATCH] net: emac: emac gigabit ethernet controller driver

On Tue, Dec 15, 2015 at 4:49 PM, Gilad Avidov <gavidov@...eaurora.org> wrote:
> On Mon, 14 Dec 2015 17:39:09 -0800
> Florian Fainelli <f.fainelli@...il.com> wrote:
>
>> On 14/12/15 16:19, Gilad Avidov wrote:
>>
>> [snip]
>>
>> > +                   "sgmii_irq";
>> > +           qcom,emac-gpio-mdc = <&msmgpio 123 0>;
>> > +           qcom,emac-gpio-mdio = <&msmgpio 124 0>;
>> > +           qcom,emac-tstamp-en;
>> > +           qcom,emac-ptp-frac-ns-adj = <125000000 1>;
>> > +           phy-addr = <0>;
>>
>> Please use the standard Ethernet PHY and MDIO device tree bindings to
>> describe your MAC to PHY connection here, that includes using a
>> phy-connection-type property to describe the (x)MII lanes.
>>
>
>
> Hi Florian,
>
> Thank you for the review.
>
> Unfortunately this Ethernet controller's PHY is non standard and fits
> poorly into the standard MDIO framework layer. Rather than read/writs
> over MDIO only, this hw have some of the PHY registers internal and
> accessed by memory mapped IO, while others are accessed over the MDIO.
> Some standard functions requires using both. Additionally a number
> of different functions are controlled from different fields of the
> same register.

Even so, the bindings should follow the standard binding for MDIO bus
whether you can use the common kernel infrastructure or not.

Having internal phy connected to external phy is pretty common for
10G. Not sure if that is what you mean here or not.

Rob
--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html