netdev - Re: [PATCH net] net: Allow flow dissector to handle non 4-byte aligned headers

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Message-ID: <56AF77C3.2010406@6wind.com>
Date:	Mon, 1 Feb 2016 16:20:35 +0100
From:	Nicolas Dichtel <nicolas.dichtel@...nd.com>
To:	Florian Fainelli <f.fainelli@...il.com>,
	Eric Dumazet <eric.dumazet@...il.com>,
	Tom Herbert <tom@...bertland.com>
Cc:	davem@...emloft.net, netdev@...r.kernel.org,
	sowmini.varadhan@...cle.com, kernel-team@...com
Subject: Re: [PATCH net] net: Allow flow dissector to handle non 4-byte
 aligned headers

Le 01/02/2016 01:39, Florian Fainelli a écrit :
> Le 31/01/2016 16:24, Eric Dumazet a écrit :
>> On Sun, 2016-01-31 at 13:37 -0800, Tom Herbert wrote:
>>> Call get_unaligned_be32 when we access 32-bit fields in
>>> __skb_flow_dissect. At the beginning check for unlikely case of
>>> 1-byte aligned packet.
>>>
>>> Note that flow_dissector may be asked to parse packet unaligned
>>> fields in two instances:
>>>
>>> 1) Packet from a driver which is aligned to Ethernet header
>>>     (2-byte alignment)
>>> 2) Parsing inner headers of a received GRE-TEB packet
>>>
>>> Testing: Ran super_netperf tests did not see a regression. This was on
>>> x86 which does not have problems with unaligned data.
>>
>> But this test is absolutely useless, what about testing arches that
>> actually care ?
>>
>> I am told all these MIPS based boxes have already not enough cpu power.
>
> How about the Cavium OCTEON family and Broadcom/Netlogic XLR/XLP, those
> are massively multi-core and MIPS64 capable, even though they may not
> always run a Linux networking stack, some do.
>
> There are also plenty of ARMv7/ARMv8 devices out there that would
> benefit from proper alignment some might end-up using mlx4/5 and intel
> cards.
There is also the tile architecture, up to 76 cores on the board I've seen. It
requires an alignment on 8!
I wonder how this case may be properly handled. A simple ipip scenario fails.