netdev - [PATCH 1/5] fsl/qe: add rx_sync and tx

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Message-ID: <1459327830-19829-1-git-send-email-qiang.zhao@nxp.com>
Date:	Wed, 30 Mar 2016 16:50:26 +0800
From:	Zhao Qiang <qiang.zhao@....com>
To:	<davem@...emloft.net>
CC:	<akpm@...ux-foundation.org>, <gregkh@...uxfoundation.org>,
	<oss@...error.net>, <xiaobo.xie@....com>,
	<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
	<linuxppc-dev@...ts.ozlabs.org>, Zhao Qiang <qiang.zhao@....com>
Subject: [PATCH 1/5] fsl/qe: add rx_sync and tx_sync for TDM mode

Rx_sync and tx_sync are used by QE-TDM mode,
add them to struct ucc_fast_info.

Signed-off-by: Zhao Qiang <qiang.zhao@....com>
---
 drivers/soc/fsl/qe/qe.c       | 6 ++++++
 include/soc/fsl/qe/qe.h       | 2 ++
 include/soc/fsl/qe/ucc_fast.h | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 709fc63..7026507 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -239,6 +239,12 @@ enum qe_clock qe_clock_source(const char *source)
 	if (strcasecmp(source, "none") == 0)
 		return QE_CLK_NONE;
 
+	if (strcmp(source, "tsync_pin") == 0)
+		return QE_TSYNC_PIN;
+
+	if (strcmp(source, "rsync_pin") == 0)
+		return QE_RSYNC_PIN;
+
 	if (strncasecmp(source, "brg", 3) == 0) {
 		i = simple_strtoul(source + 3, NULL, 10);
 		if ((i >= 1) && (i <= 16))
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 33b29ea..f918745 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -80,6 +80,8 @@ enum qe_clock {
 	QE_CLK22,		/* Clock 22 */
 	QE_CLK23,		/* Clock 23 */
 	QE_CLK24,		/* Clock 24 */
+	QE_RSYNC_PIN,		/* RSYNC from pin */
+	QE_TSYNC_PIN,		/* TSYNC from pin */
 	QE_CLK_DUMMY
 };
 
diff --git a/include/soc/fsl/qe/ucc_fast.h b/include/soc/fsl/qe/ucc_fast.h
index df8ea79..31548b7 100644
--- a/include/soc/fsl/qe/ucc_fast.h
+++ b/include/soc/fsl/qe/ucc_fast.h
@@ -120,6 +120,8 @@ struct ucc_fast_info {
 	int ucc_num;
 	enum qe_clock rx_clock;
 	enum qe_clock tx_clock;
+	enum qe_clock rx_sync;
+	enum qe_clock tx_sync;
 	u32 regs;
 	int irq;
 	u32 uccm_mask;
-- 
2.1.0.27.g96db324