netdev - RE: [PATCH] net: ethernet: renesas: sh_eth: do not access POST registers if not exist

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Message-ID: <SG2PR06MB1165DAEF1E16FFA7E2DC49308AE00@SG2PR06MB1165.apcprd06.prod.outlook.com>
Date:   Tue, 30 Aug 2016 14:16:41 +0000
From:   Chris Brandt <Chris.Brandt@...esas.com>
To:     Sergei Shtylyov <sergei.shtylyov@...entembedded.com>,
        "David S . Miller" <davem@...emloft.net>
CC:     Simon Horman <horms+renesas@...ge.net.au>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Daniel Palmer <daniel@...f.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH] net: ethernet: renesas: sh_eth: do not access POST
 registers if not exist

Hello Sergei,

On Aug 29, 2016, Sergei Shtylyov wrote:
>    SH7757 is not the only platform with TSU, there's e.g. R8A7740 ARM
> SoC which only has 1 GETHER channel...

I don't have the R8A7740 manual (R-Mobile A1) so I can't see. But even if it does not have the POST registers, it might not hurt anything.

I just looked at the RZ/A1 register space and there seems to be dummy registers in the POST1-4 area. I can write to them and read back what I wrote...which is all that the sh_eth driver cares about. I bet when the designers bring in the EtherC IP block, the entire register address is always populated with a simple latch registers. And then, if a feature is not included (like relay/POST), then nothing is hooked up on the back side of it.

So, the 'easiest' solution is to just put the registers into the sh_eth_offset_fast_rz array and not try to make things more complicated.
	[TSU_TEN]	= 0x0064,
+	[TSU_POST1]	= 0x0070,
+	[TSU_POST2]	= 0x0074,
+	[TSU_POST3]	= 0x0078,
+	[TSU_POST4]	= 0x007c,

Chris