netdev - Re: [PATCH v2] net: ethernet: renesas: sh

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Date:   Fri, 9 Sep 2016 20:49:23 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:     Chris Brandt <chris.brandt@...esas.com>,
        David Miller <davem@...emloft.net>
Cc:     Simon Horman <horms+renesas@...ge.net.au>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Daniel Palmer <daniel@...f.com>, netdev@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v2] net: ethernet: renesas: sh_eth: add POST registers for
 rz

On 09/07/2016 09:57 PM, Chris Brandt wrote:

> Due to a mistake in the hardware manual, the FWSLC and POST1-4 registers
> were not documented and left out of the driver for RZ/A making the CAM
> feature non-operational.
> Additionally, when the offset values for POST1-4 are left blank, the driver
> attempts to set them using an offset of 0xFFFF which can cause a memory
> corruption or panic.
>
> This patch fixes the panic and properly enables CAM.
>
> Reported-by: Daniel Palmer <daniel@...f.com>
> Signed-off-by: Chris Brandt <chris.brandt@...esas.com>
> ---
> v2:
> * POST registers really do exist, so just add them
> ---
>  drivers/net/ethernet/renesas/sh_eth.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
> index 1f8240a..440ae27 100644
> --- a/drivers/net/ethernet/renesas/sh_eth.c
> +++ b/drivers/net/ethernet/renesas/sh_eth.c
[...]
> @@ -2781,6 +2786,8 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp)
>  {
>  	if (sh_eth_is_rz_fast_ether(mdp)) {
>  		sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
> +		sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
> +				 TSU_FWSLC);	/* Enable POST registers */
>  		return;
>  	}

    Wait, don't you also need to write 0s to the POST registers like done at 
the end of this function?

MBR, Sergei