netdev - Re: Alignment issues with freescale FEC driver

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Message-ID: <bc19d934-f50b-50d6-0f4f-ecfcb8a2a1c9@nelint.com>
Date:   Fri, 23 Sep 2016 11:35:17 -0700
From:   Eric Nelson <eric@...int.com>
To:     Andrew Lunn <andrew@...n.ch>
Cc:     Eric Dumazet <edumazet@...gle.com>,
        Fugang Duan <fugang.duan@....com>,
        Otavio Salvador <otavio@...ystems.com.br>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        Troy Kisky <troy.kisky@...ndarydevices.com>,
        rmk+kernel@....linux.org.uk, Simone <cjb.sw.nospam@...il.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: Alignment issues with freescale FEC driver

Thanks Andrew.

On 09/23/2016 11:13 AM, Andrew Lunn wrote:
>> Since the hardware requires longword alignment for its' DMA transfers,
>> aligning the IP header will require a memcpy, right?
> 
> The vf610 FEC has an SHIFT16 bit in register ENETx_TACC, which inserts
> two padding bits on transmit. ENETx_RACC has the same.
> 
> What about your hardware?
> 

You got me with the RTFM!

>From the i.MX6DQ reference manual, bit 7 of ENET_RACC says this:

"RX FIFO Shift-16

When this field is set, the actual frame data starts at bit 16 of the first
word read from the RX FIFO aligning the Ethernet payload on a
32-bit boundary."

Same for the i.MX6UL.

I'm not sure what it will take to use this, but it seems to be exactly
what we're looking for.