netdev - Re: [PATCH net-next 1/2] net: phy: Add Wake-on-LAN driver for Microsemi PHYs.

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Message-ID: <20160928162705.GB25553@lunn.ch>
Date:   Wed, 28 Sep 2016 18:27:05 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Raju Lakkaraju <Raju.Lakkaraju@...rosemi.com>
Cc:     netdev@...r.kernel.org, f.fainelli@...il.com,
        Allan.Nielsen@...rosemi.com
Subject: Re: [PATCH net-next 1/2] net: phy: Add Wake-on-LAN driver for
 Microsemi PHYs.

> +#define MSCC_PHY_WOL_MAC_CONTROL	  27
> +#define EDGE_RATE_CNTL_POS		  5
> +#define EDGE_RATE_CNTL_MASK		  0x00E0

This patch does not require these two #defines.

Please indicate in the cover note if the patches depends on other
patches in order to cleanly apply. Or if these patches are going to
conflict with some other patches.

> +	reg_val = phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
> +	if (wol_conf->wolopts & WAKE_MAGICSECURE)
> +		reg_val |= SECURE_ON_ENABLE;
> +	else
> +		reg_val &= ~SECURE_ON_ENABLE;
> +	phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
> +
> +	if (wol_conf->wolopts & WAKE_MAGICSECURE) {
> +		reg_val = wol_conf->sopass[4] << 8;
> +		reg_val |= wol_conf->sopass[5];
> +		phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, reg_val);
> +		reg_val = wol_conf->sopass[2] << 8;
> +		reg_val |= wol_conf->sopass[3];
> +		phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, reg_val);
> +		reg_val = wol_conf->sopass[0] << 8;
> +		reg_val |= wol_conf->sopass[1];
> +		phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, reg_val);
> +	} else {
> +		phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
> +		phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
> +		phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
> +	}

Wouldn't it be better to set the password, and then enable the
password feature?

I don't know much about WOL. Hopefully Florian will add further
comments.

	 Andrew