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Date: Mon, 31 Oct 2016 19:32:30 +0100 From: Hannes Frederic Sowa <hannes@...essinduktion.org> To: Jiri Pirko <jiri@...nulli.us>, John Fastabend <john.fastabend@...il.com> Cc: Alexei Starovoitov <alexei.starovoitov@...il.com>, Thomas Graf <tgraf@...g.ch>, Jakub Kicinski <kubakici@...pl>, netdev@...r.kernel.org, davem@...emloft.net, jhs@...atatu.com, roopa@...ulusnetworks.com, simon.horman@...ronome.com, ast@...nel.org, daniel@...earbox.net, prem@...efootnetworks.com, jbenc@...hat.com, tom@...bertland.com, mattyk@...lanox.com, idosch@...lanox.com, eladr@...lanox.com, yotamg@...lanox.com, nogahf@...lanox.com, ogerlitz@...lanox.com, linville@...driver.com, andy@...yhouse.net, f.fainelli@...il.com, dsa@...ulusnetworks.com, vivien.didelot@...oirfairelinux.com, andrew@...n.ch, ivecera@...hat.com, Maciej Żenczykowski <zenczykowski@...il.com> Subject: Re: Let's do P4 On 31.10.2016 18:12, Jiri Pirko wrote: >> > >> >In the naive implementation only pipelines that map 1:1 will work. Maybe >> >this is what Alexei is noticing? > P4 is ment to program programable hw, not fixed pipeline. Is it realistic to assume that future hardware might be programmed with a proprietary (FPGA-alike) bitstream where a generic API wouldn't fit anymore? I could imagine vendors shipping a higher abstracted VHDL/Verilog compiler in the future and expect the kernel just forward it to the hardware as-is. Bye, Hannes
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