netdev - Re: [PATCH net] bgmac: stop clearing DMA receive control register right after it is set

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Message-Id: <20161031.205137.959277684113173080.davem@davemloft.net>
Date:   Mon, 31 Oct 2016 20:51:37 -0400 (EDT)
From:   David Miller <davem@...emloft.net>
To:     gospo@...adcom.com
Cc:     netdev@...r.kernel.org, hauke@...ke-m.de
Subject: Re: [PATCH net] bgmac: stop clearing DMA receive control register
 right after it is set

From: Andy Gospodarek <gospo@...adcom.com>
Date: Mon, 31 Oct 2016 13:32:03 -0400

> Current bgmac code initializes some DMA settings in the receive control
> register for some hardware and then immediately clears those settings.
> Not clearing those settings results in ~420Mbps *improvement* in
> throughput; this system can now receive frames at line-rate on Broadcom
> 5871x hardware compared to ~520Mbps today.  I also tested a few other
> values but found there to be no discernible difference in CPU
> utilization even if burst size and prefetching values are different.
> 
> On the hardware tested there was no need to keep the code that cleared
> all but bits 16-17, but since there is a wide variety of hardware that
> used this driver (I did not look at all hardware docs for hardware using
> this IP block), I find it wise to move this call up and clear bits just
> after reading the default value from the hardware rather than completely
> removing it.
> 
> This is a good candidate for -stable >=3.14 since that is when the code
> that was supposed to improve performance (but did not) was introduced.
> 
> Signed-off-by: Andy Gospodarek <gospo@...adcom.com>
> Fixes: 56ceecde1f29 ("bgmac: initialize the DMA controller of core...")
> Cc: Hauke Mehrtens <hauke@...ke-m.de>

Applied and queued up for -stable, thanks.