netdev - Re: [net-next 1/2] net: ethernet: slicoss: add slicoss gigabit ethernet driver

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Message-ID: <20161115215907.GF23231@lunn.ch>
Date:   Tue, 15 Nov 2016 22:59:07 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Lino Sanfilippo <LinoSanfilippo@....de>
Cc:     Florian Fainelli <f.fainelli@...il.com>, davem@...emloft.net,
        charrer@...critech.com, liodot@...il.com,
        gregkh@...uxfoundation.org, devel@...verdev.osuosl.org,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [net-next 1/2] net: ethernet: slicoss: add slicoss gigabit
 ethernet driver

> The link state is retrieved by a command to the application processor that is running 
> on the network card. Also the register to set the phy configuration is write-only, so
> it is not even possible to do the usual mdio bit-banging in the Phy read() and write()
> functions (however there seems to be another application processor command reserved 
> for retrieving the PHY settings, but I have not tried it yet). 

>> +  			val = MII_BMCR << 16 | SLIC_PCR_AUTONEG |
>> +		     	         SLIC_PCR_AUTONEG_RST;
>> +			slic_write(sdev, SLIC_REG_WPHY, val);

This actually looks a lot like an MDIO write operation. The upper 16
bits are the register, and the lower 16 bits are the data. What you
don't have is the address. But maybe it is limited to one address.

If the processor command reserved for read works in a similar way, you
have enough to do an MDIO bus.

> Please also note that I do not have any datasheets or other documentation for the hardware, 
> all I have as a reference is the driver code in staging. So I do not know which 
> PHYs are actually used (the comments in the code mention Marvell and Cicada but this is
> not very specific).

If you can get the read working look at registers 2 and 3. Compare
what you get with the values at the end of marvell.c.

     Andrew