netdev - Re: [PATCH net 1/2] r8152: fix the sw rx checksum is unavailable

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Message-Id: <20161124.121140.2054576632424977475.davem@davemloft.net>
Date:   Thu, 24 Nov 2016 12:11:40 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     mlord@...ox.com
Cc:     hayeswang@...ltek.com, netdev@...r.kernel.org,
        nic_swsd@...ltek.com, linux-kernel@...r.kernel.org,
        linux-usb@...r.kernel.org
Subject: Re: [PATCH net 1/2] r8152: fix the sw rx checksum is unavailable

From: Mark Lord <mlord@...ox.com>
Date: Thu, 24 Nov 2016 11:43:53 -0500

> So even if this were a platform memory coherency issue, one should
> still never see ASCII data at the beginning of an rx buffer.

I'm not so convinced, since this is the kind of random corruption one
would expect to see when dealing with virtual caches that have
aliasing or similar issues.

Writes to address X that show up at address Y or not at all are
precisely the signature of virtual cache aliasing problems.

Is it a case of the chip writing to X but the cpu is still seeing
stale data from a previous CPU store?

For NFS the cpu is writing into the page cache, so we know that
cpu side stores are where the ASCII text is coming from.

Now is the r8152 buffer one that the USB host controller is DMA'ing
into directly, or is it one that SWIOMMU or similar bounce buffering
is copying into?  In the latter case we are doing cpu stores into
the area and the writes aren't coming from the device.